gEDA-user: HELP with Icarus Verilog, 0.7!

["Samuel A. Falvo II" <sam.falvo@falvotech.com>]

Greetings.

This is my first time using Verilog, and unfortunately, I'm not having 
much luck trying to get several modules to talk to each other via a 
tri-stated bus interface.  If anyone can offer some tips or tricks that 
is portable to other Verilog environments, that'd be great.

I can't disclose my modules here, due to their size.  But maybe I can 
host the heads of each module.  Here is the head of the module giving me 
problems:

module Kestrel_UART_RX( RXD, RBF, _RES, RXC, DB, _RXDATAL_E, _RXDATAH_E, 
_RXMASKL_E, _RXMASKH_E );
 input RXD, _RES, RXC, _RXDATAL_E, _RXDATAH_E, _RXMASKL_E, _RXMASKH_E;
 output RBF;
 inout [7:0] DB;   // <-- I need this to be a real tri-state bus

 reg RBF;
 reg [7:0] DBout;
 reg [15:0] shiftRegister;
 reg inFrame;
 wire rxc_div_8;

 reg [15:0] rxdata;
 reg [15:0] rxmask;
 wire [15:0] startDetect;
 wire rd;

 assign startDetect = rxmask & shiftRegister;
 assign rd = ( _RXDATAL_E === 0 ) || ( _RXDATAH_E === 0 );
 assign DB = rd? DBout : 8'bzzzzzzzz;  // <-- technique seems to work in 
TB, but not here.  Why?

Whenever a write the the RXMASK* registers is performed, as evidenced by 
_RXMASK*_E signals going low, the value loaded into the registers are 
always 16'hxxxx or 16'hxxXX or some such (what is the difference between 
x and X in this context?), as reported by $display.  Here is the 
assignment code for those registers (yes, the value of DB is "valid" in 
the testbench before asserting the appropriate register enables):

 // Writable UART registers.

 always @(_RXMASKL_E) begin
  if( _RXMASKL_E === 0 ) begin
   rxmask = { rxmask[15:8], DB[7:0] };
  end
 end

 always @(_RXMASKH_E) begin
  if( _RXMASKH_E === 0 ) begin
   rxmask = { DB[7:0], rxmask[7:0] };
  end
 end

Any ideas why rxmask is being assigned undefined values?

Thanks for your help.  It's greatly appreciated.

--
Samuel A. Falvo II