Re: gEDA-user: HELP with Icarus Verilog, 0.7!

[Berni Joss <berni.joss@hispeed.ch>]

On Sun, Apr 04, 2004 at 09:18:24PM -0800, Samuel A. Falvo II wrote:
>  assign rd = ( _RXDATAL_E === 0 ) || ( _RXDATAH_E === 0 );
>  assign DB = rd? DBout : 8'bzzzzzzzz;  // <-- technique seems to work in 
> TB, but not here.  Why?

<snip> 
</snip> 

>  always @(_RXMASKL_E) begin
>   if( _RXMASKL_E === 0 ) begin
>    rxmask = { rxmask[15:8], DB[7:0] };
>   end
>  end
> 
>  always @(_RXMASKH_E) begin
>   if( _RXMASKH_E === 0 ) begin
>    rxmask = { DB[7:0], rxmask[7:0] };
>   end
>  end
> 
> Any ideas why rxmask is being assigned undefined values?

I'm not a verilog expert and haven't used Icarus yet, but ... could it be that
your DB is not being assigned zzz "fast enough"?

It is my understanding that the sequence of execution (in the sequential
simulator) of the "parallel" blocks is not defined, i.e. after _RXDATAL_E goes
0, which block will the simulator execute first: the "assign DB = ..." or the "always ... rxmask = ..." ?

Also, if I understand this correctly your "alwasy @(_RXMASK... rxmask = ..."
blocks will latch on the falling edge of _RXMASKx_E, because the always @()
triggers on a change (edge) and not on the level. I may misunderstand you code
snippet, but possibly you intended to describe a latch rather than a negative
edge clocked flip-flop ...

Berni