Re: gEDA-user: HELP with Icarus Verilog, 0.7!

[Berni Joss <berni.joss@hispeed.ch>]

On Tue, Apr 06, 2004 at 11:57:09AM -0700, Samuel A. Falvo II wrote:
> Why can't I write this instead:
> 
>   always @(posedge CLK_I) begin
>     if( RXMASKL_E )  // changed to active high signal for convenience
>       rxmask[7:0] <= DAT_I[7:0];
>     if( RXMASKH_E )
>       rxmask[15:8] <= DAT_I[7:0];
>   end
> 
>   always @(RST)  // level sensitive, asynchronous reset
>     if( ~_RST )
>       rxmask <= 16'h0040;
>   end

If you expect an implementation of rxmask with flip-flops having an
asynchronous clear/set input, then it may be better to have a single always
block. This is based on my limited experience with synthesizeing vhdl with
synplicity a couple of years ago ... so possibly not applicable in you
situation.

Berni