Re: gEDA-user: HELP with Icarus Verilog, 0.7!

[John Griessen <john_g@cibolo.com>]

It could matter.    

A reset is a well behaved logic function like AND or OR, so you could say it as a assignment of a math 
function when you ant behavioral code.  In your example, you assign reset directly to a wire, so 
the only math that wires do, is what you get. 
Verilog wires give  0, 1, or X usually, and sometimes they can deal in drive strengths to yield a 
weak 1 or weak 0...   and I've forgotten if Z state is a built in, and can't help you with the 
High Z tristate bus driver example.

If there is no Z state primitive for verilog wires/registers/busses, you could make a 
not-intended-to-be-synthesized test module that models the tristate driver and yet drives more than 
one wire to encode the state of the real tristate wire.   All such tristate non-synthesizable 
driver and receiver models would have to be stripped out and replaced with ports that 
go to "analog-modeling" zone.   I bet there's a way to make calls to a module in icarus verilog
that contains a new kind of verilog primitive written in c.   You could make a tristate 
driver, receiver, and wire to extend verilog if there is no primitive for that.

When you write verilog, you need to go into 
a non-procedural-programming mode.  Whenever something is mutually exclusive like the
 states a bus/register/wire can be in, you need to be certain you are telling it only one 
state to be in at a time, and the best way to do this is to put all the choices in a case
 statement, or if that's not possible, create some kind of assertion checker that goes 
through that same logical list of mutually exclusive conditions so it will find that if you 
made that mistake.   Otherwise that kind of mistake can be hard to locate later.   
Sure, you'll see X's, but the source of them will be upstream...maybe far upstream...


John
On Tue, 2004-04-06 at 13:57, Samuel A. Falvo II wrote:
> I re-read this four times, and I can't make out what you are saying.  
What do you mean by "same destination register?"  And why would it 
matter if they appeared in multiple always-blocks?  I have one always 
block for the reset, and one for the register writes.  Is this what 
you're referring to, possible contention of writing to the registers 
while reseting?
-- 
John Griessen    Cibolo Design       Austin Texas,   linux counter #249315