Re: gEDA-user: Finished drawing two sided board in PCB. Any comment?

[9000 VAX <vax9000@xxxxxxxxx>]

On 4/29/05, Stuart Brorson <sdb@xxxxxxxxxx> wrote:
> Hi Vax 9000 --
> 
> I looked at your Gerbers using GCPrevue.  It's a very impressive
> board, in terms of density.  Also, the horizontal/vertical routing
> scheme on different used is very professional looking.  Good job!

Thank you!

> 
> Comments:
> 
> *  YOu didn't include the top or bottom soldermask layers in your zip
> file. One big gotcha is if the soldermask relief (i.e. clearance)
> doesn't adequately keep soldermask away from the pins and pads.  We
> can't check this if the Gerbers aren't there.  (Not that I want to
> make extra work for myself . . . . . . 

I uploaded a new file that zipped every gbr files. I will check the
clearance against the manufacturer's requrement (33each.com for
prototyping).

> 
> *  You might want to back the plane layers away from all board edges by
> 50 or 100 mils or more.  There are some places where the planes went
> right to the end of the board.  Inadequate clearance can lead to
> shorts when the panel is broken apart into individual boards.

I will correct this mistake.

> 
> *  A big gotcha is if your pads aren't adequately larger than the
> associated drills.  El-cheapo board houses don't drill exactly on hole
> center.  I have used pads at least 20 mils larger than drill
> diameters, and this is barely adequate sometimes.  Check this against
> the fab drawing (also not in the zip file).

All pads are 55mil/29mil and  all vias are 46mil/29mil(power) and
36mil/20mil(signal).
I will double check with their requirement.

> 
> *  I seem to recall that this is a low speed board.  Since there is no
> GND or power plane possible with a two layer board, you might be
> susceptable to signal integrity problems like crosstalk, particularly
> if you are using fast parts.  Make sure your design is robust against
> glitches and crosstalk.  This problem becomes more acute as you go to
> higher and higher speeds.

All signals that are connected with ribbon cables are slow (driven by
SCSI II chip, 74LS and 7406). All fast signal traces driven by 74lvt
are short. And the CPLD can be programmed to slow down output signals.

> 
> Just some thoughts.  I'll bet that others here have other observations
> to make.

Thank you for your comments. They are very helpful as your previous one.

vax, 9000

> 
> Stuart