Re: gEDA-user: Keep Out Layer/Line

[DJ Delorie <dj@xxxxxxxxxxx>]

> > We already know antisilk won't work.
>
> This is vendor dependent. APL's pcb shop uses GCCAM to process all 
> artwork, and anti-silk works just fine, for example.

Well, true, but I don't think it's something PCB should lead the user
to expect to always work.  For example, we clipped silk over pads,
both on-screen and in the gerbers, so the user didn't realize that
they had a problem until the boards came back from the fab or were put
on hold.

Given that, I don't see how we can add an anti-silk feature when we
know that a nontrivial subset of the fabs will reject or misfab the
board.

Now, perhaps we could default to disabling it, and let the vendor file
enable it for vendors we know support it.  I'm not worried about the
internal support in pcb, I'm worried about setting the user up for
failure.

PS: What's APL?