Re: gEDA-user: A couple o' questions

[sdb@xxxxxxxxxx (Stuart Brorson)]

> DRC is perhaps useful for large digital designs, but it is more  
> trouble than it's worth for small analog designs. The pintypes are  
> designed for digital, and often it isn't obvious what pintype you  
> want in analog.  For example, for current mode interfaces the rules  
> about connecting inputs and outputs in parallel are reversed. There's  
> no way to distinguish between power *sources* and power *sinks*. Of  
> course you can designate everything passive, but then it's useless  
> (and that's still extra work).
> 
> Despite these limitations, gnetlist does a hard sell for DRC, as if  
> it was going to find lots of common problems when it really only  
> finds a restricted subset. We have newbies sweating to get DRC to  
> work for things like power supplies. That's silly.

I must say that I agree with this assessment.  DRC checking a
schematic -- particularly an analog one -- is a nice thing to do, but
the results should be taken with a grain of salt.  As you say, we
unfortunately have newbies who are sweating bullets to make every last
DRC go away.  This is silly.  Also, they are doing something
potentially very hazardous:  Putting the NC symbol onto pins,
potentially leading to *real* problems on their boads down the pike.
That defeats the purpose of DRC checking.

I will say that I've kept my mouth shut about this since Carlos is
leading the developement charge, and I respect, admire, and appreciate
his work.  I'm glad somebody is developing a DRC checker, and when
people make contributions to the project, they should be applauded and
encouraged!  However, in this small case I do think that the business
of having newbies put NC symbols on their pins should be stopped until
the larger fix -- i.e. making NC not netlist anywhere -- is
implemented.  Carlos, what do you think? 

I'll also say that the place where DRC checking is *critical* is in
checking your PCB's layout against your fab vendor's DFM rules.  Keys
to that are things like:

Min trace width/space
Min annular ring (i.e. min pad size over drill size)
Min soldermask clearance from pads
Min soldermask bridge width
Checking for metal slivers

I know that PCB does some checks (min trace width/space), but am not
so sure about min annular ring, a problem which is currently hammering
me in a big way on a non-gEDA board.  :-(

If somebody were to write an open-source equivalent of Genesys 2000
(Valor), which is a CAM/DFM tool used by PCB fabs, they'd find
themselves the object of a lot of adoration from happy users!

Stuart