gEDA-user: Polygon clearance for pairs in PCB

[Karel Kulhavy <clock@xxxxxxxxxxxxx>]

I suggest that a feature to disable clearing certain polygons by certain
vias and lines to be implemented. The user would select a via and
polygon or line and polygon and then press some magic menu entry and it
would add a marker to the polygon or to the via that this particular
pair should not clear.

The manual overlapping by polygons is more work. And often it's messy,
resulting in jagge edges.

CL<