gEDA-user: iverilog vs. $realtime?

[Dan McMahill <dan@xxxxxxxxxxxx>]

I'm trying to use $realtime for some stuff with the 20060409 verilog 
snapshot.  I'm getting some funny results with $realtime and I'm not 
sure if its me doing something stupid or it its a bug in verilog.  FWIW, 
verilog-XL gives the answer I think I should get.

`timescale 1ns/10ps

module test();
   reg ck;
   integer cnt;
   real    tval;

   initial begin
      ck <= 0;
      cnt <= 0;
      tval <= 0.0;
   end


   always #2 ck <= !ck;


   always @(posedge ck) begin
      cnt <= cnt + 1;
      tval <= $realtime;
      $display ("tval = %g\n", tval);

      if (cnt >= 5) begin
	 $finish;
      end
   end

endmodule // test


verilog-XL gives

tval = 0
tval = 2
tval = 6
tval = 10
tval = 14
tval = 18

icarus verilog gives:

tval = 0
tval = 2
tval = 2
tval = 6
tval = 6
tval = 10


I made up this test case after having problems with the following from 
my real code:

Assertion failed: now.high == 0, file sys_time.c, line 126
Abort - core dumped

I can make that go away by commenting out a line where I do

	x <= $realtime;  // x is a real

-Dan