gEDA-user: Re: iverilog: Parameters of Parameters

[Stephen Williams <steve@xxxxxxxxxx>]

lingwitt-Bdlq13kUjeyLZ21kGMrzwg@xxxxxxxxxxxxxxxx wrote:
>     module A (input theInput, output theOutput);
>         parameter delay = 2;
> 
>         // Do something
> 
>     endmodule
> 
>     module B (input theInput, output theOutput);
>         parameter delay = a.delay + 5;
> 
>         A a(theInput, theOutput);
> 
>         // Do something
> 
>     endmodule
> 
> The idea is that I'd like to know some kind of
> total accumulative delay during elaboration.

 [ ... ]

> Basically, I'm whining for a feature.

I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Modelsim handles it) seems plausible.
This is a good candidate for the Feature Request list, I think.

Be warned that bug reports are getting far more of my time then
feature requests, but at least if they are in the list they will
not get forgotten.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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