gEDA-user: iverilog: Parameters of Parameters

[lingwitt@xxxxxxxxxxxxx]

This is relevant:
http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/ 
3bc899be1008b8e5/8c0086d88906db19#8c0086d88906db19

Hello.
Consider:

    module A (input theInput, output theOutput);
        parameter delay = 2;

        // Do something

    endmodule

    module B (input theInput, output theOutput);
        parameter delay = a.delay + 5;

        A a(theInput, theOutput);

        // Do something

    endmodule

The idea is that I'd like to know some kind of
total accumulative delay during elaboration.

Unfortunately, the previous example isn't valid
syntax according to iverilog:

	error: parameter value must be a constant expression.

However, ModelSim apparently allows this (see the link above).

Basically, I'm whining for a feature.

Thanks.


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