Re: gEDA-user: Lines which are not clears poligon

[Tamas Szabo <sza2king@xxxxxxxxxxx>]

DJ Delorie wrote:
>> The latter one have a strange behavior. The most problematic that some 
>> of the lines not clears the rectangle used for filling the unused area 
>> by copper. Unfortunately DRC does not show any error or warning although 
>> there a many short circuit due to the rectangle.
> 
> Looks like a bug to me.  Ben?  Can you look at this one?

That's why I want to check whether there is overlapped lines. Maybe 
those can confuse pcb.

> 
>> Additionally the copper (size: 0.1mm, 0.1mm, w-0.1mm, h-0.1mm) surrounds 
>> the mounting hole in case of the control.pcb, but not for the io.pcb.
> 
> Use the thermal tool to change that.

Thanks! Now definitely better:-)

> 
>> Furthermore am I right that ClrFlag(selection, join) should switch on 
>> clearance for all selected lines? But it seems it is not working for me. 
> 
> It should.

Something I do wrong surely. SetFlag(selection, join) and 
ClrFlag(selection, join) are not changing the behavior but Shift-J works 
  as expected.

What I do: turn off all layers except Component side, select all visible 
object. :ClrFlag(selection, join), create rectangle from 0,0 to w,h but 
the lines on which join turned on connects the rectangle, lines with 
join turned off are not connect to rectangle. Shift-J changes behavior 
to the opposite correctly. What do I wrong?

> 
> 
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