gEDA-user: Lines which are not clears poligon

[Tamas Szabo <sza2king@xxxxxxxxxxx>]

Hello,

Could anyone help me?

I have two identical size board with identical coords for mounting holes.

http://web.t-online.hu/sza2webacces/gEDA/control.pcb
http://web.t-online.hu/sza2webacces/gEDA/io.pcb

The latter one have a strange behavior. The most problematic that some 
of the lines not clears the rectangle used for filling the unused area 
by copper. Unfortunately DRC does not show any error or warning although 
there a many short circuit due to the rectangle.

Additionally the copper (size: 0.1mm, 0.1mm, w-0.1mm, h-0.1mm) surrounds 
the mounting hole in case of the control.pcb, but not for the io.pcb.

What is the difference?

Furthermore am I right that ClrFlag(selection, join) should switch on 
clearance for all selected lines? But it seems it is not working for me. 
What do I wrong?

Thx,

/sza2


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