Re: gEDA-user: DRC stuff

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Thu, 2009-04-02 at 00:25 +0000, Kai-Martin Knaak wrote:
> On Wed, 01 Apr 2009 19:52:49 -0400, gene glick wrote:
> 
> > 1. What does "potential for broken trace" mean?
> 
> There are tracks that overlap less than the minimum recommended value. 
> This value can be configured in 
> 	preferences - sizes

I still see PCB complain about these in instances I can't understand
what it is griping about. Might be a bug. KMK's explanation of the
feature's intention is correct though.

Aside from the historical reason for its existence (back when each line
was drawn individually by the photo-plotter, features had to have an
overlap in case of registration issues), it helps catch places where you
might have two correctly sized lines just touching at their circular
capped ends. (Leaving a piece of copper less than the allowed thickness,
but which would not be caught by the DRC rule which checks the line
widths).

> > 2. Why does it report so many DRC errors, "copper areas too close", when
> >   I routed with 10 mil space and list DRC as 10 mil clearance?

Assuming there are no real violations on the board, it could be a
rounding error, or a inclusive / exclusive test bug. Try setting your
DRC rules to allow 9.9 mil spacing.. does the reports go away?

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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