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Re: gEDA-user: un-tented vias

On Fri, 16 Apr 2010 12:34:29 -0400, DJ Delorie wrote:

> You could modify the sources to do that, but there's no runtime option
> to do so.

Where would the setting be located in the source?


> You could do this:
> 
> Enable soldermask layer
> Select All
> :ChangeClearSize(SelectedVias,=1,mil) :MinMaskGap(SelectedVias,=3,mil)

Hmm. Quite a hassle when typed into the GUI. It might be a job for a non 
interactive action script, though.


> Or write a quick plug-in to do it

Where would I look for information on pcb plug-ins? The manual does not 
seem to know the keyword. 

---<)kaimartin(>---
-- 
Kai-Martin Knaak                                  tel: +49-511-762-2895
UniversitÃt Hannover, Inst. fÃr Quantenoptik      fax: +49-511-762-2211	
Welfengarten 1, 30167 Hannover           http://www.iqo.uni-hannover.de
GPG key:    http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get



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