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gEDA-user: Database on symbols, footprints and other (was "Re: gattrib")
Hi,
since the stuff I managed to layout with your help is soldered now and
shining brightly,
I got some time, to have a look at my attempt to a database. So I have
to take levels
of abstraction and their naming serious.
John Doty wrote:
On Apr 27, 2010, at 12:26 PM, Mike Bushroe wrote:
Not because of the bugs I ran into but since choosing a footprint is
a difficult process in it self I was longing for a footprint
browser.
My personal view is that schematics should use the conventions in the gEDA documentation:
http://geda.seul.org/wiki/geda:pcb_footprint_naming_conventions
Agree with adhering to the convention, don't agree with the convention.
The simple
reason for my critics on the convention is case-use: studies in the aera
of teletyping
have shown, that lower case is faster to read than uppercase. That and
the limit
on bandwidth is why teletypes used all lowercase letters. Then computers
appeared
on the sceen and some sales-managers found, that upper case letters
"look more professional" than lowercase letters. That and the limit on
bandwidth
is, why the 1st computer terminals used all uppercase ;-)
Now compare the following:
PART 1: AXHN868X888
PART 2: AXBN868X888
PART 3: AXHN8688X88
vs.
part 1: axhn868x888
part 2: axbn868x888
part 3: axhn8688x88
I don't want to suggest to deviate from well known acronyms like DIN,
but why must we use
an uppercase X for separation of dimensions and the like?
(And what are "Basic SMT semiconductors"? surface mounted tevices ?)
Some of the convention-based names seem to contain spaces. From what I read,
the trailing non-space groups are actually macro parameters for the
m4-processor.
This should be dealt with somehow I think, since it clashes with easy
file treatment
and newlib is the way to go, isn't it?
These refer to the device, not the pattern of copper on the board. The pattern of copper corresponding to a given device footprint should be chosen in the layout process, because it depends (like other layout parameters) on the manufacturing processes.
For me a device is a MAX232 or HCTL-2016, both sitting in a DIL-16 package
(among other possibilties).
So actually the convention above would describe canonical names for
packages.
So far in all datasheets I read, the copper pattern if at all is
specified with dimensions
and no mention is made of any manufacturing process (or I just ignored it,
knowing my hand-soldering capabilities being far from um-precision).
Still I want the database to provide for such detail and distinguish between
"package" and "footprint".
A database-driven tool that maps device footprints into layout footprints would be useful. We could have databases for various requirement sets here.
One thing that comes to mind with integrating simulator-models in the
database is, that
the package for a given device influences parameters like parasitic
capacitance of pins.
The more so does the copper pattern of the pads including layers below
the actual pad.
- would we want to address this in a database? Where does it end?
(if this sounds weird, go to www.analog.com, search for "rarely asked
questions" and then find
RAQ_capacitycectomy.pfd - it's fun to read IMO)
Keeping the responsibility for this out of gschem avoids unnecessary complication and facilitates design reuse: the schematic should be as free as possible from dependencies on the layout and manufacturing processes.
Agree.
Armin
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