Re: gEDA-user: Save/Restart Features in Verilog 2001?

["Mike Jarabek" <mjarabek@istop.com>]

Paul Michael Hartke <phartke@Stanford.EDU> said:

> > phartke@Stanford.EDU said:
> > > However, I see that annex is prefaced with "The system tasks and
> > > functions described in this annex are for informative purposes only
> > > and are not part of the IEEE standard Verilog HDL."
> > 
> > Ah, I missed that whole section:-)
> > 
> > Still, $save/$incsave/$restart are pretty unlikely to be addressed
> > by me unless there is a pretty major clamor over it. I have other
> > more pressing issues to deal with.

If I remember correctly, way back, these functions worked by core-dumping the
simulator, and then re-loading the core image at will to restart the
simulation where it was stopped.  A global variable or two were probably set
just before the core dump to enable the reloaded image to know it was
re-loaded. ( This, of course, has the nasty problem that such dirty tricks are
not always portable across platforms...  ;-)


-- 
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                              Mike Jarabek
                                FPGA/ASIC Designer
   http://www.doncaster.on.ca/~mjarabek
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