gEDA-user: ANN: New version of Verilog Netlister in CVS

["Mike Jarabek" <mjarabek@istop.com>]

Hi all,

	I have enhanced the Verilog netlister to allow for some more interesting
simulation possibilities.  I have added the ability for the netlister to
output Verilog `escaped' identifiers.  This facility allows arbitrary
identifiers to be accepted by a Verilog simulator and be used in a
simulation.  This can, for example, be used to build up a simualation of a
bunch of TTL chips connected together in a circuit, to do a board level
simulation of your project.  I have tried this with Icarus Verilog, and it
works.  The only hangup is that you will have to create `models' for each of
the TTL chips, that match up the pin numbers to functionality inside the
chip.  I can provide an example of how to do this for anyone who is
interested.  (I have a little demo circuit that works with Icarus Verilog.)

	My changes are now in CVS.  Happy netlisting!

-- 
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                              Mike Jarabek
                                FPGA/ASIC Designer
   http://www.doncaster.on.ca/~mjarabek
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---- Latest README.verilog ----

	This is the fifth release of the Verilog netlister for gEDA.

	New in this release:

	1) Escaped Verilog identifiers.

	To facilitate board level simulations, the Verilog netlister now
outputs `escaped' Verilog identifiers for any net, port or instance name
that does not appear to be a valid Verilog identifier.  In this way, 
chips with numbered pins can be netlisted and models constructed to run
digital simulations of complete circuits.