Re: gEDA-user: iVerilog -tfpga: if-else errors?

[Stephen Williams <steve@icarus.com>]

Mike Butts wrote:
> In iVerilog, synthesizing even a simple if-else results in errors:
> For example, this simple FF with clock enable and asynch reset from the 
> Alternate Verilog FAQ:
>
> module dff_cke (data, clock, reset, cke, q);
>     // port list
>     input   data, clock, reset, cke;
>     output  q;
>
>     // reg / wire declaration for outputs / inouts
>     reg     q;
>
>     // logic begins here
>     always @(posedge clock or negedge reset)
>         if (reset == 0)
>             q <= 1'b0;
>         else if (cke == 1'b1)
>             q <= data;
> endmodule
It should be able to handle this, but sure 'nuf I get the same
error you get. File a bug report?

BTW the problem is that it is not detecting the reset input.
It should. Needs fixing.

--
Steve Williams                "The woods are lovely, dark and deep.
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