gEDA-user: iVerilog -tfpga: if-else errors?

[Mike Butts <mbutts@realizer.com>]

In iVerilog, synthesizing even a simple if-else results in errors:
For example, this simple FF with clock enable and asynch reset from the 
Alternate Verilog FAQ:

module dff_cke (data, clock, reset, cke, q);
    // port list
    input   data, clock, reset, cke;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // logic begins here
    always @(posedge clock or negedge reset)
        if (reset == 0)
            q <= 1'b0;
        else if (cke == 1'b1)
            q <= data;
endmodule

$ iverilog -tfpga -parch=virtex dff_cke.v
dff_cke.v:11: error: Events are unaccounted for in process synthesis.
dff_cke.v:13: error: Asynchronous if statement is missing the else clause.
1 error(s) in post-elaboration processing.
Command signaled: c:\iverilog\lib\ivl\ivlpp  -L -D__ICARUS__=1 
-fc:\DOCUME~1\Mike\LOCALS~1\Temp\ivrlg2b1d  | c:\iverilog\lib\ivl\ivl 
-Cc:\DOCUME~1\Mike\LOCALS~1\Temp\ivrlh2b1d -g3.0      -parch=virtex -tdll 
-fDLL=c:\iverilog\lib\ivl\fpga.tgt -Fsynth2 -Fsynth -Fsyn-rules -Fcprop 
-Fnodangle -oa.out -- -

I compiled the same file with Xilinx ISE 5.2 and XST synthesizes it just fine.

I'm running Icarus version 0.7 20030116 from a Windows XP command line.

Is there a flag or setting I'm missing?  Surely iVerilog can synthesize 
flip-flops?  Thanks!

  --Mike