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Re: gEDA-user: Array initialization in Verilog?



On 8/9/05, Harold D. Skank <skank54@xxxxxxxxx> wrote:
> People,
> 
> I need an array of 120, 1-bit variables for a Verilog variable.  I can
> create the array OK, but how do I give it an initial value?
> 
> 	Harold Skank

IMHO this is not a Verilog forum. comp.lang.verilog is a 
better place to ask *only* verilog related question.

Krishanu