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Re: gEDA-user: Array initialization in Verilog?

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Krishanu Debnath wrote:
| On 8/9/05, Harold D. Skank <skank54@xxxxxxxxx> wrote:
|
|>People,
|>
|>I need an array of 120, 1-bit variables for a Verilog variable.  I can
|>create the array OK, but how do I give it an initial value?
|>
|>	Harold Skank
|
|
| IMHO this is not a Verilog forum. comp.lang.verilog is a
| better place to ask *only* verilog related question.
|
| Krishanu
|

To be clear, Icarus Verilog questions are OK (even encouraged)
on this mailing list, but generic Verilog questions are indeed
slightly out of place here.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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