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Re: gEDA-user: bypass caps

I updated the board online, adding five 10uF 0805s around the board.
One near each incoming power, two in the middle, and one at the other
end of the board.  Plus the one 10uF on the 3.3v regulator.


I feel like I'm beating this horse far beyond the point where it's
already dead. . . . . .

But I looked at your most recent layout, and another question occurred
to me:  Is there a reason you are using long, spindly traces [1] for
VCC/GND, and not using great big polygons (areafills) [2]?  For SI, it
would be far, far better to have large PWR/GND plane areas separated
by small voids than have long, spindly traces like you have now.  It
would certainly cut way down on teh inductance you have in your
PWR/GND network . . . .

Stuart

[1]  Yes, I realize they are 12 or 20 mil (or somethign like that),
but they are not great big areafills.  And since they are long,
isolated traces, they will have inductance.

[2]  Besides the fact that doing areafills using PCB is still a PITA,
that is . . . .



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