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gEDA-user: pcb: I'm having trouble getting traces to contact some pads
Hi (again),
I'm pretty new at using pcb and have encountered a problem I can't
figure out. My problem is that for several components, pcb won't allow
me to draw a trace line all the way to the pad. I can draw the trace
almost to the pad, but then it refuses to go any farther.
Here's how I got into this, and what I know so far:
Using gschem I created a .sch file for the circuit I'd like to
fabricate, and used gsch2pcb to create .net and .pcb files. My circuit
has several .sym and footprint (newlib) files I made myself.
The versions are:
gschem 20060824
gnetlist 20060824
pcb 20060822
I am using a pretty much up-to-date FC5.
For some components, pcb will not allow me to connect a trace to the
pads when coming from outside the pad inward. In some cases, though, I
can connect to the pad if I start the trace on the pad and then move
outward.
The rat's nest pcb generates doesn't connect to these problem
components.
I think the problem must be related to DRC because I can work around it
by manually editing the .pcb file to change the PCB Flags from 0xd0 to
0x50. The offending components are still shunned by the rat's nest,
however, and later in the process I get warnings about pins connected by
a trace being shorted together.
When I use some of the troublesome components in a separate, simple,
circuit everything seems to work fine.
Interestingly, two different resistors use the same footprint, but one
is included in the rat's nest and the other is not.
Running gnetlist -g drc2 on my .sch file gives only one error:
Checking nets with only one connection...
ERROR: Net 'unnamed_net3' is connected to only one pin: X4:4
This pin is connected to a no connection symbol on the schematic, so I
think it should be OK.
Most of the troublesome components are ones with footprints or/and .sym
files I made myself. I must be doing something wrong. Can anyone help
me? I'll attach the .sch and .net and .pcb files to this email.
Thanks.
Frazer
v 20060824 1
C 55000 54500 1 180 1 4N25-1.sym
{
T 56800 52700 5 10 1 1 180 0 1
refdes=X3
T 55000 54500 5 10 0 1 0 0 1
value=A4N25
T 55000 54500 5 10 0 1 0 0 1
file=../../../4n25.spi
T 55000 54500 5 10 0 1 0 0 1
footprint=DIL 6 300
}
N 54600 54200 55000 54200 4
{
T 53300 54100 13 10 1 1 0 0 1
netname=Gnd
}
N 57100 53300 57100 54200 4
C 56300 50800 1 90 0 resistor-1.sym
{
T 56700 51500 5 10 1 1 180 0 1
refdes=R2
T 56400 51100 5 10 1 1 0 0 1
value=50k
T 56300 50800 5 10 0 1 0 0 1
footprint=R025
}
C 55700 50800 1 90 0 zener-1.sym
{
T 55000 50900 5 10 1 1 0 0 1
refdes=X2
T 55400 50600 5 10 1 1 270 0 1
value=BZX85C15
T 55700 50800 5 10 0 1 180 0 1
file=../../../84095.SP3
T 55700 50800 5 10 0 1 180 0 1
footprint=Zener
}
C 55000 50800 1 90 0 capacitor-1.sym
{
T 54500 51400 5 10 1 1 180 0 1
refdes=C1
T 54600 51200 5 10 1 1 180 0 1
value=10uF
T 55000 50800 5 10 0 1 0 0 1
footprint=CAP-CB
}
N 54800 51700 56200 51700 4
N 60200 52500 59700 52500 4
N 60200 52100 59700 52100 4
C 59800 54500 1 0 0 vdd-1.sym
N 60200 53300 60000 53300 4
N 60000 53300 60000 54500 4
C 63700 51800 1 270 0 resistor-1.sym
{
T 64100 51400 5 10 1 1 0 0 1
refdes=Rsense
T 64100 51200 5 10 1 1 0 0 1
value=0.050
T 63700 51800 5 10 0 1 0 0 1
footprint=LOB-1
}
N 63800 52000 63800 51800 4
N 62200 52100 62400 52100 4
N 62400 52100 62400 51800 4
N 57100 54200 60000 54200 4
C 54600 51700 1 0 0 vdd-1.sym
N 59700 52500 59700 50800 4
N 60000 54200 61200 54200 4
N 63800 53000 63800 54200 4
C 67200 52200 1 90 0 capacitor-1.sym
{
T 66700 52800 5 10 1 1 180 0 1
refdes=Cstore
T 66300 52400 5 10 0 0 90 0 1
symversion=0.1
T 66300 52400 5 10 1 1 0 0 1
value=2uF
T 67200 52200 5 10 0 1 0 0 1
footprint=Cstore
}
C 68000 52200 1 90 0 resistor-1.sym
{
T 68700 52800 5 10 1 1 180 0 1
refdes=Rstore
T 68200 52400 5 10 1 1 0 0 1
value=1Meg
T 68000 52200 5 10 0 1 0 0 1
footprint=RstoreR3
}
N 67000 53100 67900 53100 4
N 67000 52200 67900 52200 4
C 64900 54100 1 0 0 resistor-1.sym
{
T 65100 54600 5 10 1 1 0 0 1
refdes=Req2
T 65100 54400 5 10 1 1 0 0 1
value=10K
T 64900 54100 5 10 0 1 0 0 1
footprint=R025
}
N 62100 54200 64900 54200 4
{
T 62700 55500 13 10 1 1 0 0 1
netname=SWout
}
N 65800 54200 67500 54200 4
{
T 67100 55600 13 10 1 1 0 0 1
netname=CAPout
}
N 67500 50800 67500 52200 4
{
T 67200 49700 13 10 1 1 0 0 1
netname=CAPin
}
N 63000 54200 63000 54600 4
N 67500 53100 67500 54600 4
C 62200 53200 1 0 0 nc-right-1.sym
C 63200 52000 1 0 0 irfpg50.sym
{
T 64100 52500 5 10 1 1 0 0 1
refdes=X1
T 62800 52000 5 10 1 1 0 0 1
value=IRFPG50
T 63200 52000 5 10 0 1 0 0 1
file=/usr/share/gEDA/models/spice3/InternationalRectifier/irfpg50.spi
T 63200 52000 5 10 0 1 0 0 1
footprint=TO247
}
C 60200 51700 1 0 0 Si9910.sym
{
T 61900 53800 5 10 1 1 0 6 1
refdes=X4
T 60200 51700 5 10 0 1 0 0 1
file=../../../Si9910.spi
T 60200 51700 5 10 0 1 0 0 1
value=Si9910
T 60200 51700 5 10 0 1 0 0 1
footprint=DIL 8 300
}
C 54900 53600 1 180 0 spice-subcircuit-IO-1.sym
{
T 54000 53200 5 10 1 1 0 0 1
pinnumber=1
T 54900 53600 5 10 0 1 0 0 1
refdes=U2
T 54900 53600 5 10 0 1 0 0 1
footprint=CONNECTOR 1 2
}
C 54800 54500 1 180 0 spice-subcircuit-IO-1.sym
{
T 53800 54100 5 10 1 1 0 0 1
pinnumber=2
T 54800 54500 5 10 0 1 0 0 1
refdes=U1
T 54800 54500 5 10 0 1 0 0 1
footprint=CONNECTOR 1 2
}
C 63500 51000 1 270 0 spice-subcircuit-IO-1.sym
{
T 63800 50000 5 10 1 1 0 0 1
pinnumber=3
T 63500 51000 5 10 0 1 0 0 1
refdes=U3
T 63500 51000 5 10 0 1 0 0 1
footprint=CONNECTOR 1 2
}
C 67200 51000 1 270 0 spice-subcircuit-IO-1.sym
{
T 67500 50000 5 10 1 1 0 0 1
pinnumber=5
T 67200 51000 5 10 0 1 0 0 1
refdes=U4
T 67200 51000 5 10 0 1 0 0 1
footprint=CONNECTOR 1 2
}
C 63300 54400 1 90 0 spice-subcircuit-IO-1.sym
{
T 62900 55300 5 10 1 1 0 0 1
pinnumber=4
T 63300 54400 5 10 0 1 0 0 1
refdes=U5
T 63300 54400 5 10 0 1 0 0 1
footprint=CONNECTOR 1 2
}
C 67800 54400 1 90 0 spice-subcircuit-IO-1.sym
{
T 67400 55300 5 10 1 1 0 0 1
pinnumber=6
T 67800 54400 5 10 0 1 0 0 1
refdes=U6
T 67800 54400 5 10 0 1 0 0 1
footprint=CONNECTOR 1 2
}
N 63800 50900 63800 50800 4
C 62300 52400 1 0 0 resistor-1.sym
{
T 62500 52900 5 10 1 1 0 0 1
refdes=Rgate
T 62600 52700 5 10 1 1 0 0 1
value=100
T 62300 52400 5 10 0 1 0 0 1
footprint=0.125W_Carbon_Resistor
}
N 62200 52900 62200 52500 4
{
T 62100 52300 13 10 1 1 0 0 1
netname=X4out
}
N 62200 52500 62300 52500 4
N 54700 53300 55000 53300 4
{
T 53500 53200 13 10 1 1 0 0 1
netname=Vin
}
C 54200 55000 1 0 0 spice-directive-1.sym
{
T 54300 55400 5 10 0 1 0 0 1
refdes=A1
T 54300 55100 5 10 1 1 0 0 1
value=.SUBCKT HVModule2 Vin Gnd SWin SWout CAPin CAPout
}
C 57800 51100 1 90 0 resistor-1.sym
{
T 58200 51700 5 10 1 1 180 0 1
refdes=R1
T 57900 51400 5 10 1 1 0 0 1
value=30k
T 57800 51100 5 10 0 1 0 0 1
footprint=R025
}
N 57700 51100 57700 50800 4
C 65100 52100 1 90 0 capacitor-1.sym
{
T 65700 52700 5 10 1 1 180 0 1
refdes=Csnub
T 64200 52300 5 10 0 0 90 0 1
symversion=0.1
T 65200 52300 5 10 1 1 0 0 1
value=10nF
T 65100 52100 5 10 0 1 0 0 1
footprint=Csnub
}
N 62400 51800 64900 51800 4
N 64900 51800 64900 52100 4
N 63800 53300 64900 53300 4
N 64900 53300 64900 53000 4
N 54800 50800 63800 50800 4
{
T 63600 49700 13 10 1 1 0 0 1
netname=SWin
}
N 57700 52900 57700 52000 4
N 57100 52900 60200 52900 4
{
T 57500 53100 13 10 1 1 0 0 1
netname=X3out
}
C 61200 54100 1 0 0 resistor-1.sym
{
T 61500 54600 5 10 1 1 0 0 1
refdes=R3
T 61400 54400 5 10 1 1 0 0 1
value=1Meg
T 61200 54100 5 10 0 1 0 0 1
footprint=RstoreR3
}
C 60000 47500 1 0 0 cvstitleblock-1.sym
{
T 60600 47900 5 10 1 1 0 0 1
date=Aug. 15, 2006
T 64500 47900 5 10 1 1 0 0 1
rev=2.1
T 64600 47600 5 10 1 1 0 0 1
auth=F. Williams
T 60800 48200 5 10 1 1 0 0 1
fname=hvmodule.sch
T 61400 48600 5 14 1 1 0 4 1
title=HV Module
}
X4out Rgate-1 X4-8 X4-7
unnamed_net3 X4-4
unnamed_net2 Rgate-2 X1-1
SWout R3-2 U5-1 Csnub-2 X1-2 Req2-1
CAPout U6-1 Req2-2 Rstore-2 Cstore-2
CAPin U4-1 Rstore-1 Cstore-1
unnamed_net1 Csnub-1 X4-5 X1-3 Rsense-1
SWin Rsense-2 U3-1 R1-1 X4-6 X4-1 C1-1 X2-1 R2-1
X3out R1-2 X4-2 X3-6
Vdd C1-2 X2-2 R2-2 R3-1 X4-3 X3-4 X3-5
Gnd U1-1 X3-2
Vin U2-1 X3-1
# release: pcb 1.6.3
PCB("" 6000 5000)
Grid(10 0 0)
Cursor(10 270 3)
Flags(0x000000d0)
Groups("1,2,3,s:4,5,6,c:7:8:")
Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
Element["" "Cstore" "Cstore" "2uF" 50000 50000 0 0 0 100 ""]
(
Pin[0 -144000 20000 2000 20600 4500 "" "1" "pin"]
Pin[0 143000 20000 2000 20600 4500 "" "2" "pin"]
ElementLine [69000 -107000 69000 106000 1000]
ElementLine [0 106000 0 126000 1000]
ElementLine [-69000 106000 69000 106000 1000]
ElementLine [-69000 -107000 -69000 106000 1000]
ElementLine [0 -107000 0 -127000 1000]
ElementLine [-69000 -107000 69000 -107000 1000]
)
Element["" "RstoreR3" "R3" "1Meg" 50000 85000 0 0 0 100 ""]
(
Pin[0 -55000 5000 2000 5600 3000 "1" "1" "pin"]
Pin[0 55000 5000 2000 5600 3000 "2" "2" "pin"]
ElementLine [-7000 -43000 6000 -43000 1000]
ElementLine [6000 -43000 7000 -43000 1000]
ElementLine [7000 -43000 7000 43000 1000]
ElementLine [-7000 -43000 -7000 43000 1000]
ElementLine [7000 43000 -7000 43000 1000]
ElementLine [0 -45000 0 -50000 1000]
ElementLine [0 45000 0 50000 1000]
)
Element(0x00000000 "0.125W_Carbon_Resistor" "Rgate" "100" 500 500 56 -138 0 100 0x00000000)
(
Pin(0 0 60 30 60 28 "" "1" 0x00000001)
Pin(0 -300 60 30 60 28 "" "2" 0x00000001)
ElementLine (0 -50 0 -90 10)
ElementLine (40 -90 -40 -90 10)
ElementLine (-40 -90 -40 -210 10)
ElementLine (-40 -210 40 -210 10)
ElementLine (40 -210 40 -90 10)
ElementLine (0 -210 0 -250 10)
)
# retain backwards compatibility to older versions of PKG_DIL
# which did not have ,, args
Element(0x00 "DIL-8-300" "X4" "Si9910" 220 100 3 100 0x00)
(
Pin(50 50 60 28 "1" 0x101)
Pin(50 150 60 28 "2" 0x01)
Pin(50 250 60 28 "3" 0x01)
Pin(50 350 60 28 "4" 0x01)
Pin(350 350 60 28 "5" 0x01)
Pin(350 250 60 28 "6" 0x01)
Pin(350 150 60 28 "7" 0x01)
Pin(350 50 60 28 "8" 0x01)
ElementLine(0 0 0 400 10)
ElementLine(0 400 400 400 10)
ElementLine(400 400 400 0 10)
ElementLine(0 0 150 0 10)
ElementLine(250 0 400 0 10)
ElementArc(200 0 50 50 0 180 10)
Mark(50 50)
)
Element(0x00 "R025" "R2" "50k" 120 30 0 100 0x00)
(
Pin(0 50 50 20 "1" 0x101)
Pin(400 50 50 20 "2" 0x01)
ElementLine(100 0 300 0 20)
ElementLine(300 0 300 100 20)
ElementLine(300 100 100 100 20)
ElementLine(100 100 100 0 20)
ElementLine(0 50 100 50 20)
ElementLine(300 50 400 50 20)
Mark(0 50)
)
# retain backwards compatibility to older versions of PKG_DIL
# which did not have ,, args
Element(0x00 "DIL-6-300" "X3" "A4N25" 220 100 3 100 0x00)
(
Pin(50 50 60 28 "1" 0x101)
Pin(50 150 60 28 "2" 0x01)
Pin(50 250 60 28 "3" 0x01)
Pin(350 250 60 28 "4" 0x01)
Pin(350 150 60 28 "5" 0x01)
Pin(350 50 60 28 "6" 0x01)
ElementLine(0 0 0 300 10)
ElementLine(0 300 400 300 10)
ElementLine(400 300 400 0 10)
ElementLine(0 0 150 0 10)
ElementLine(250 0 400 0 10)
ElementArc(200 0 50 50 0 180 10)
Mark(50 50)
)
Element(0x00 "R025" "R1" "30k" 120 30 0 100 0x00)
(
Pin(0 50 50 20 "1" 0x101)
Pin(400 50 50 20 "2" 0x01)
ElementLine(100 0 300 0 20)
ElementLine(300 0 300 100 20)
ElementLine(300 100 100 100 20)
ElementLine(100 100 100 0 20)
ElementLine(0 50 100 50 20)
ElementLine(300 50 400 50 20)
Mark(0 50)
)
Element["" "LOB-1" "Rsense" "0.050" 50000 50000 0 0 0 100 ""]
(
Pin[0 -66000 6000 2000 6600 3500 "1" "1" "pin"]
Pin[0 66000 6000 2000 6600 3500 "2" "2" "pin"]
ElementLine [-7000 -20000 7000 -20000 1000]
ElementLine [-7000 -20000 -7000 20000 1000]
ElementLine [-7000 20000 7000 20000 1000]
ElementLine [7000 20000 7000 -20000 1000]
ElementLine [0 -26000 0 -57000 1000]
ElementLine [0 26000 0 56000 1000]
)
Element["" "Zener" "X2" "BZX85C15" 19685 39764 0 0 0 100 ""]
(
Pin[0 -20079 6000 2000 6600 3500 "2" "2" "pin"]
Pin[0 20079 6000 2000 6600 3500 "1" "1" "pin"]
ElementLine [-5118 -8268 5118 -8268 1000]
ElementLine [-5118 8267 5118 8267 1000]
ElementLine [-5118 -8268 -5118 8267 1000]
ElementLine [5118 -8268 5118 8267 1000]
ElementLine [0 -8268 0 -14173 1000]
ElementLine [0 8267 0 14173 1000]
ElementLine [-5118 7480 4331 7480 1000]
ElementLine [-5118 6693 5118 6693 1000]
ElementLine [-5118 5905 4331 5905 1000]
)
Element["" "Csnub" "Csnub" "10nF" 19685 63780 0 0 0 100 ""]
(
Pin[0 -44095 7969 2000 8569 3500 "1" "1" "pin"]
Pin[0 44488 7969 2000 8569 3500 "2" "2" "pin"]
ElementLine [-16929 -51969 16929 -51969 1000]
ElementLine [-16929 52362 16929 52362 1000]
ElementLine [16929 -51969 16929 52362 1000]
ElementLine [-16929 52362 -16929 -51969 1000]
)
Element(0x00 "CONNECTOR-1-2" "U6" "unknown" 260 0 3 100 0x00)
(
Pin(50 50 60 30 "1" 0x101)
Pin(150 50 60 30 "2" 0x01)
ElementLine(0 0 0 100 20)
ElementLine(0 100 200 100 20)
ElementLine(200 100 200 0 20)
ElementLine(200 0 0 0 20)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
Mark(50 50)
)
Element(0x00 "TO247" "X1" "IRFPG50" 690 50 3 100 0x00)
(
Pin(96 130 100 60 "1" 0x101)
Pin(315 130 100 60 "2" 0x01)
Pin(534 130 100 60 "3" 0x01)
ElementLine(0 0 0 210 20)
ElementLine(0 210 630 210 20)
ElementLine(630 210 630 0 20)
ElementLine(630 0 0 0 20)
ElementLine(0 50 630 50 10)
ElementLine(240 0 240 50 10)
ElementLine(390 0 390 50 10)
Mark(96 270)
)
Element(0x00 "CONNECTOR-1-2" "U5" "unknown" 260 0 3 100 0x00)
(
Pin(50 50 60 30 "1" 0x101)
Pin(150 50 60 30 "2" 0x01)
ElementLine(0 0 0 100 20)
ElementLine(0 100 200 100 20)
ElementLine(200 100 200 0 20)
ElementLine(200 0 0 0 20)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
Mark(50 50)
)
Element(0x00 "CONNECTOR-1-2" "U4" "unknown" 260 0 3 100 0x00)
(
Pin(50 50 60 30 "1" 0x101)
Pin(150 50 60 30 "2" 0x01)
ElementLine(0 0 0 100 20)
ElementLine(0 100 200 100 20)
ElementLine(200 100 200 0 20)
ElementLine(200 0 0 0 20)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
Mark(50 50)
)
Element["" "CAP-CB" "C1" "10uF" 39000 76000 0 0 0 100 ""]
(
Pin[1000 -56000 6000 2000 6600 3500 "1" "1" "pin"]
Pin[1000 56000 6000 2000 6600 3500 "2" "2" "pin"]
ElementLine [-15000 -36000 17000 -36000 1000]
ElementLine [-15000 36000 16000 36000 1000]
ElementLine [-15000 -36000 -15000 36000 1000]
ElementLine [17000 -36000 17000 36000 1000]
ElementLine [1000 -38000 1000 -48000 1000]
ElementLine [1000 38000 1000 49000 1000]
)
Element(0x00 "CONNECTOR-1-2" "U3" "unknown" 260 0 3 100 0x00)
(
Pin(50 50 60 30 "1" 0x101)
Pin(150 50 60 30 "2" 0x01)
ElementLine(0 0 0 100 20)
ElementLine(0 100 200 100 20)
ElementLine(200 100 200 0 20)
ElementLine(200 0 0 0 20)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
Mark(50 50)
)
Element["" "RstoreR3" "Rstore" "1Meg" 50000 85000 0 0 0 100 ""]
(
Pin[0 -55000 5000 2000 5600 3000 "1" "1" "pin"]
Pin[0 55000 5000 2000 5600 3000 "2" "2" "pin"]
ElementLine [-7000 -43000 6000 -43000 1000]
ElementLine [6000 -43000 7000 -43000 1000]
ElementLine [7000 -43000 7000 43000 1000]
ElementLine [-7000 -43000 -7000 43000 1000]
ElementLine [7000 43000 -7000 43000 1000]
ElementLine [0 -45000 0 -50000 1000]
ElementLine [0 45000 0 50000 1000]
)
Element(0x00 "CONNECTOR-1-2" "U2" "unknown" 260 0 3 100 0x00)
(
Pin(50 50 60 30 "1" 0x101)
Pin(150 50 60 30 "2" 0x01)
ElementLine(0 0 0 100 20)
ElementLine(0 100 200 100 20)
ElementLine(200 100 200 0 20)
ElementLine(200 0 0 0 20)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
Mark(50 50)
)
Element(0x00 "R025" "Req2" "10K" 120 30 0 100 0x00)
(
Pin(0 50 50 20 "1" 0x101)
Pin(400 50 50 20 "2" 0x01)
ElementLine(100 0 300 0 20)
ElementLine(300 0 300 100 20)
ElementLine(300 100 100 100 20)
ElementLine(100 100 100 0 20)
ElementLine(0 50 100 50 20)
ElementLine(300 50 400 50 20)
Mark(0 50)
)
Element(0x00 "CONNECTOR-1-2" "U1" "unknown" 260 0 3 100 0x00)
(
Pin(50 50 60 30 "1" 0x101)
Pin(150 50 60 30 "2" 0x01)
ElementLine(0 0 0 100 20)
ElementLine(0 100 200 100 20)
ElementLine(200 100 200 0 20)
ElementLine(200 0 0 0 20)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
Mark(50 50)
)
Layer(1 "solder")
(
)
Layer(2 "GND-sldr")
(
)
Layer(3 "Vcc-sldr")
(
)
Layer(4 "component")
(
)
Layer(5 "GND-comp")
(
)
Layer(6 "Vcc-comp")
(
)
Layer(7 "unused")
(
)
Layer(8 "unused")
(
)
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