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gEDA-user: gschem2pcb netlist problem

To: geda-user@xxxxxxxx
Subject: gEDA-user: gschem2pcb netlist problem
From: Philipp Klaus Krause <pkk@xxxxxxx>
Date: Sun, 05 Aug 2007 20:00:17 +0200
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I have a problem in a recently created schematic:
gschem2pcb creates a netlist where +5V and GND are connected together.
I do not see such a connection in the schematic (5V stuff is in the
lower left corner only, VCC is +3.3V)

gschem2pcb worked initially, then I realized that pins on the voltage
regulator were wrong in the symbol. I changed the pin numbers in the
symbol, now there's the problem. I already tried deleting and
reinserting the voltage regulatgor symbol, but it didn't help.

Philipp

v 20070626 1
C 0 0 1 0 0 title-A2.sym
C 2000 2500 1 90 0 capacitor-1.sym
{
T 1300 2700 5 10 0 0 90 0 1
device=CAPACITOR
T 1500 2700 5 10 1 1 90 0 1
refdes=C1
T 1100 2700 5 10 0 0 90 0 1
symversion=0.1
T 2000 2500 5 10 0 0 90 0 1
footprint=0805
}
C 4400 2500 1 90 0 capacitor-1.sym
{
T 3700 2700 5 10 0 0 90 0 1
device=CAPACITOR
T 3900 2700 5 10 1 1 90 0 1
refdes=C2
T 3500 2700 5 10 0 0 90 0 1
symversion=0.1
T 4400 2500 5 10 0 0 90 0 1
footprint=0805
}
C 21400 6900 1 0 0 resistor-2.sym
{
T 21800 7250 5 10 0 0 0 0 1
device=RESISTOR
T 21600 7200 5 10 1 1 0 0 1
refdes=R1
T 21400 6900 5 10 0 0 0 0 1
footprint=0805
}
C 19400 10300 1 0 0 XC9536PC44_CFG.sym
{
T 19700 10850 5 10 1 1 0 2 1
refdes=U1
T 19700 10650 5 10 1 1 0 2 1
device=XC9536
T 19600 9850 5 10 0 0 0 8 1
footprint=QFP44_10
}
C 600 0 1 0 0 XC9536PC44_PWR.sym
{
T 900 550 5 10 1 1 0 2 1
refdes=U1
T 900 350 5 10 1 1 0 2 1
device=XC9536
T 800 -450 5 10 0 0 0 8 1
footprint=QFP44_10
}
C 19700 6900 1 0 0 24Cxx-1.sym
{
T 20000 8050 5 10 0 0 0 0 1
device=24Cxx
T 20700 7900 5 10 1 1 0 0 1
refdes=U3
T 20000 8250 5 10 0 0 0 0 1
footprint=SO8M
}
C 21500 13200 1 0 0 testpt-1.sym
{
T 21600 13600 5 10 1 1 0 0 1
refdes=TP?
T 21900 14100 5 10 0 0 0 0 1
device=TESTPOINT
T 21900 13900 5 10 0 0 0 0 1
footprint=none
}
C 22000 13200 1 0 0 testpt-1.sym
{
T 22100 13600 5 10 1 1 0 0 1
refdes=TP?
T 22400 14100 5 10 0 0 0 0 1
device=TESTPOINT
T 22400 13900 5 10 0 0 0 0 1
footprint=none
}
C 22500 13200 1 0 0 testpt-1.sym
{
T 22600 13600 5 10 1 1 0 0 1
refdes=TP?
T 22900 14100 5 10 0 0 0 0 1
device=TESTPOINT
T 22900 13900 5 10 0 0 0 0 1
footprint=none
}
C 23000 13200 1 0 0 testpt-1.sym
{
T 23100 13600 5 10 1 1 0 0 1
refdes=TP?
T 23400 14100 5 10 0 0 0 0 1
device=TESTPOINT
T 23400 13900 5 10 0 0 0 0 1
footprint=none
}
C 20200 14300 1 0 0 testpt-1.sym
{
T 20300 14700 5 10 1 1 0 0 1
refdes=TP?
T 20600 15200 5 10 0 0 0 0 1
device=TESTPOINT
T 20600 15000 5 10 0 0 0 0 1
footprint=none
}
C 20800 14900 1 0 0 testpt-1.sym
{
T 20900 15300 5 10 1 1 0 0 1
refdes=TP?
T 21200 15800 5 10 0 0 0 0 1
device=TESTPOINT
T 21200 15600 5 10 0 0 0 0 1
footprint=none
}
N 5300 14600 1000 14600 4
N 5500 15400 1000 15400 4
N 5700 14200 1000 14200 4
N 5900 13400 1000 13400 4
N 5100 12600 1000 12600 4
N 6300 11800 1000 11800 4
N 1000 11000 6500 11000 4
N 1000 13800 11100 13800 4
N 5300 13500 11100 13500 4
N 5500 13200 11100 13200 4
N 5700 12900 11100 12900 4
N 5900 12600 11100 12600 4
N 5100 12300 11100 12300 4
N 6300 12000 11100 12000 4
N 6500 11700 11100 11700 4
C 12800 -200 1 90 0 XC9536PC44_IO.sym
{
T 12250 100 5 10 1 1 90 2 1
refdes=U1
T 12450 100 5 10 1 1 90 2 1
device=XC9536
T 13250 0 5 10 0 0 90 8 1
footprint=QFP44_10
}
C 13552 7200 1 0 1 27C2001-1.sym
{
T 13152 15200 5 10 0 0 0 6 1
footprint=PLCC32
T 13152 14800 5 10 0 0 0 6 1
device=27C2001
T 13152 14500 5 10 1 1 0 6 1
refdes=U2
T 13152 16700 5 10 0 0 0 6 1
symversion=1.0
}
C 1174 3300 1 0 1 connector30-2.sym
{
T 374 15900 5 10 1 1 0 0 1
refdes=CONN1
T 774 15850 5 10 0 0 0 6 1
device=CONNECTOR_30
T 774 16050 5 10 0 0 0 6 1
footprint=CVCON
}
C 4000 4100 1 0 0 vcc-2.sym
N 3800 3800 4200 3800 4
N 4200 3400 4200 4100 4
N 1800 2200 1800 2500 4
N 3000 3200 3000 2200 4
N 1200 2200 4200 2200 4
N 1200 2200 1200 4200 4
N 1000 4200 1200 4200 4
C 4100 1500 1 0 0 gnd-1.sym
N 4200 1800 4200 2500 4
N 12000 1100 12000 1300 4
N 12000 1300 13000 1300 4
C 12732 1300 1 180 1 vcc-2.sym
N 13400 8100 13800 8100 4
N 13800 7800 13400 7800 4
N 4700 2000 17200 2000 4
N 17200 2100 4700 2100 4
N 4700 2200 17200 2200 4
N 17200 2300 4700 2300 4
N 4700 2400 17200 2400 4
N 17200 2500 4700 2500 4
N 4700 2600 17200 2600 4
N 17200 3000 4700 3000 4
N 4700 2900 17200 2900 4
N 17200 2800 4700 2800 4
N 4700 2700 17200 2700 4
N 4700 3100 17200 3100 4
N 4700 3300 17200 3300 4
N 17200 3400 4700 3400 4
N 4700 3500 17200 3500 4
N 17200 3600 4700 3600 4
N 4700 3700 17200 3700 4
N 4700 4100 17200 4100 4
N 4700 4000 17200 4000 4
N 17200 3900 4700 3900 4
N 4700 3800 17200 3800 4
N 4700 4500 17200 4500 4
N 17200 4600 4700 4600 4
N 4700 4700 17200 4700 4
N 4700 4800 17200 4800 4
N 5000 1100 5000 2000 4
N 5200 1100 5200 2100 4
N 5400 1100 5400 2200 4
N 5600 1100 5600 2300 4
N 5800 1100 5800 2400 4
N 6000 1100 6000 2500 4
N 6200 1100 6200 2600 4
N 6400 1100 6400 2700 4
N 6600 1100 6600 2800 4
N 6800 1100 6800 2900 4
N 7000 1100 7000 3000 4
N 7200 1100 7200 3100 4
N 7400 1100 7400 3200 4
N 7600 1100 7600 3300 4
N 7800 1100 7800 3400 4
N 8000 1100 8000 3500 4
N 8200 1100 8200 3600 4
N 8400 1100 8400 3700 4
N 8600 1100 8600 3800 4
N 8800 1100 8800 3900 4
N 9000 1100 9000 4000 4
N 9200 1100 9200 4100 4
N 9400 1100 9400 4200 4
N 9600 1100 9600 4300 4
N 9800 1100 9800 4400 4
N 10000 1100 10000 4500 4
N 10200 1100 10200 4600 4
N 10400 1100 10400 4700 4
N 10600 1100 10600 4800 4
N 10800 1100 10800 4900 4
N 11000 1100 11000 5000 4
N 11200 1100 11200 5100 4
N 11400 1100 11400 5200 4
N 11600 1100 11600 5300 4
N 6500 2000 6500 11700 4
N 6300 2100 6300 12000 4
N 6100 13800 6100 2200 4
N 5900 2300 5900 13400 4
N 5700 2400 5700 14200 4
N 5500 2500 5500 15400 4
N 5300 2600 5300 14600 4
N 5100 2700 5100 12600 4
N 13800 5300 13800 8100 4
N 14300 5200 14300 8700 4
N 14300 8700 13400 8700 4
N 13400 9000 14400 9000 4
N 14400 9000 14400 5100 4
N 14500 5000 14500 9300 4
N 14500 9300 13400 9300 4
N 13400 9600 14600 9600 4
N 14600 9600 14600 4900 4
N 14700 4800 14700 9900 4
N 14700 9900 13400 9900 4
N 13400 10200 14800 10200 4
N 14800 10200 14800 4700 4
N 13400 7500 14200 7500 4
N 14200 7500 14200 4600 4
N 11700 14400 11800 14400 4
N 11800 14400 11800 14700 4
N 1000 5000 4300 5000 4
N 4300 5000 4300 5800 4
N 4300 5800 6700 5800 4
N 6700 5800 6700 2800 4
N 1000 7000 6900 7000 4
N 1000 8600 7100 8600 4
N 7100 8600 7100 3000 4
N 6900 2900 6900 7000 4
N 7300 3100 7300 15000 4
N 7300 15000 1000 15000 4
N 4700 5300 21800 5300 4
N 4700 5200 21800 5200 4
N 4700 5100 21800 5100 4
N 4700 5000 21800 5000 4
N 4700 4900 21800 4900 4
N 4700 4400 21800 4400 4
N 4700 4300 21800 4300 4
C 19400 6700 1 0 0 gnd-1.sym
N 19500 7000 19500 7600 4
N 19500 7600 19700 7600 4
N 19700 7400 19500 7400 4
N 19500 7200 19700 7200 4
N 21100 7000 21100 4400 4
N 21000 7200 21200 7200 4
N 21200 7200 21200 4300 4
N 21000 7400 21300 7400 4
N 21300 7400 21300 4200 4
N 4700 4200 21800 4200 4
C 22300 7200 1 0 0 vcc-2.sym
N 21000 7000 21400 7000 4
N 22300 7000 22500 7000 4
N 22500 7000 22500 7200 4
C 2200 1400 1 0 0 vcc-2.sym
C 300 300 1 0 0 gnd-1.sym
N 2200 1000 2400 1000 4
N 2400 1000 2400 1400 4
N 2400 1200 2200 1200 4
N 400 600 400 1200 4
N 400 1200 600 1200 4
N 600 1000 400 1000 4
N 400 800 600 800 4
N 4700 3200 21800 3200 4
C 11400 14400 1 90 0 vcc-2.sym
N 12100 14400 12400 14400 4
N 13400 13800 15900 13800 4
N 13400 13500 16000 13500 4
N 13400 13200 16100 13200 4
N 13400 12900 16200 12900 4
N 1000 13000 8000 13000 4
N 8000 13000 8000 15000 4
N 8000 15000 15900 15000 4
N 15900 3200 15900 15000 4
N 1000 12200 5000 12200 4
N 5000 12200 5000 12400 4
N 5000 12400 8100 12400 4
N 8100 12400 8100 15100 4
N 8100 15100 16000 15100 4
N 16000 3300 16000 15100 4
N 1000 11400 8200 11400 4
N 8200 11400 8200 15200 4
N 8200 15200 16100 15200 4
N 16100 3400 16100 15200 4
N 1000 9800 8300 9800 4
N 8300 9800 8300 15300 4
N 8300 15300 16200 15300 4
N 16200 3500 16200 15300 4
N 1000 9000 8400 9000 4
N 8400 9000 8400 15400 4
N 8400 15400 16300 15400 4
N 16300 12600 13400 12600 4
N 1000 7400 8500 7400 4
N 8500 7400 8500 15500 4
N 8500 15500 16400 15500 4
N 16400 12300 13400 12300 4
N 1000 6600 8600 6600 4
N 8600 6600 8600 15600 4
N 8600 15600 16500 15600 4
N 16500 12000 13400 12000 4
N 1000 5800 8700 5800 4
N 8700 5800 8700 15700 4
N 8700 15700 16600 15700 4
N 16600 3900 16600 15700 4
N 16600 11700 13400 11700 4
N 11400 14600 12400 14600 4
N 12400 14600 12400 14400 4
N 1000 4600 1200 4600 4
N 1200 4600 1200 5500 4
N 1200 5500 8800 5500 4
N 8800 5500 8800 15800 4
N 8800 15800 16700 15800 4
N 16700 11400 13400 11400 4
N 13400 11100 16800 11100 4
N 16800 15900 8900 15900 4
N 8900 5400 8900 15900 4
N 8900 5400 1000 5400 4
N 14100 4500 14100 14700 4
N 11800 14700 14100 14700 4
N 16300 3600 16300 15400 4
N 16400 3700 16400 15500 4
N 16500 3800 16500 15600 4
N 16800 15900 16800 11100 4
N 16700 11400 16700 15800 4
N 1000 9400 9000 9400 4
N 9000 9400 9000 16000 4
N 9000 16000 16900 16000 4
N 16900 16000 16900 10800 4
N 16900 10800 13400 10800 4
N 13400 10500 17000 10500 4
N 17000 16100 9100 16100 4
N 9100 10200 9100 16100 4
N 9100 10200 1000 10200 4
N 1000 6200 11800 6200 4
N 11800 6200 11800 4000 4
N 17000 4100 17000 16100 4
N 1000 3800 2200 3800 4
N 1800 3400 1800 3800 4
C 2200 3200 1 0 0 LM3480IM3-3.3-1.sym
{
T 3800 4500 5 10 0 0 0 0 1
device=3480IM3-3.3
T 3600 4200 5 10 1 1 0 6 1
refdes=U4
T 2200 3200 5 10 0 0 0 0 1
footprint=SOT23
}

v 20070626 1
T 400 600 9 8 1 0 0 0 1
IN
T 948 600 9 8 1 0 0 0 1
OUT
T 900 100 9 8 1 0 0 0 1
3480IM3-3.3
B 300 300 1000 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1600 1300 5 10 0 0 0 0 1
device=3480IM3-3.3
T 656 401 9 8 1 0 0 0 1
GND
P 300 600 0 600 1 0 1
{
T 100 650 5 8 1 1 0 0 1
pinnumber=2
T 100 650 5 8 0 0 0 0 1
pinseq=2
}
P 800 0 800 300 1 0 0
{
T 700 100 5 8 1 1 0 0 1
pinnumber=3
T 700 100 5 8 0 0 0 0 1
pinseq=3
}
P 1300 600 1600 600 1 0 1
{
T 1430 650 5 8 1 1 0 0 1
pinnumber=1
T 1430 650 5 8 0 0 0 0 1
pinseq=1
}
T 1400 1000 8 10 1 1 0 6 1
refdes=U?
T 1600 1100 5 10 0 0 0 0 1
pins=3
T 1600 900 5 10 0 0 0 0 1
net=GND:2

v 20061020 1
B 300 600 400 1000 3 0 0 0 0 0 0 -1 -1 -1 -1 -1
T 300 550 5 10 1 1 0 2 1
refdes=U?
T 300 350 5 10 1 1 0 2 1
device=XC9536
T 200 550 5 10 0 0 0 8 1
copyright=2007 Ben Jackson
T 200 350 5 10 0 0 0 8 1
author=Ben Jackson
T 200 150 5 10 0 0 0 8 1
uselicense=unlimited
T 200 -50 5 10 0 0 0 8 1
distlicense=GPL
T 200 -250 5 10 0 0 0 8 1
description=Xilinx XC9536
T 200 -450 5 10 0 0 0 8 1
footprint=PLCC 44
P 700 1400 1000 1400 1 0 1
{
T 650 1400 5 8 1 1 0 7 1
pinlabel=TCK
T 750 1425 5 8 1 1 0 0 1
pinnumber=17
T 750 1425 5 8 0 1 0 0 1
pinseq=9
}
P 700 1200 1000 1200 1 0 1
{
T 650 1200 5 8 1 1 0 7 1
pinlabel=TDI
T 750 1225 5 8 1 1 0 0 1
pinnumber=15
T 750 1225 5 8 0 1 0 0 1
pinseq=10
}
P 700 1000 1000 1000 1 0 1
{
T 650 1000 5 8 1 1 0 7 1
pinlabel=TDO
T 750 1025 5 8 1 1 0 0 1
pinnumber=30
T 750 1025 5 8 0 1 0 0 1
pinseq=11
}
P 700 800 1000 800 1 0 1
{
T 650 800 5 8 1 1 0 7 1
pinlabel=TMS
T 750 825 5 8 1 1 0 0 1
pinnumber=16
T 750 825 5 8 0 1 0 0 1
pinseq=12
}

v 20061020 1
B 300 600 700 7400 3 0 0 0 0 0 0 -1 -1 -1 -1 -1
T 300 550 5 10 1 1 0 2 1
refdes=U?
T 300 350 5 10 1 1 0 2 1
device=XC9536
T 200 550 5 10 0 0 0 8 1
copyright=2007 Ben Jackson
T 200 350 5 10 0 0 0 8 1
author=Ben Jackson
T 200 150 5 10 0 0 0 8 1
uselicense=unlimited
T 200 -50 5 10 0 0 0 8 1
distlicense=GPL
T 200 -250 5 10 0 0 0 8 1
description=Xilinx XC9536
T 200 -450 5 10 0 0 0 8 1
footprint=PLCC 44
P 1000 7800 1300 7800 1 0 1
{
T 950 7800 5 8 1 1 0 7 1
pinlabel=IO
T 1050 7825 5 8 1 1 0 0 1
pinnumber=1
T 1050 7825 5 8 0 1 0 0 1
pinseq=9
}
P 1000 7600 1300 7600 1 0 1
{
T 950 7600 5 8 1 1 0 7 1
pinlabel=IO
T 1050 7625 5 8 1 1 0 0 1
pinnumber=2
T 1050 7625 5 8 0 1 0 0 1
pinseq=10
}
P 1000 7400 1300 7400 1 0 1
{
T 950 7400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 7425 5 8 1 1 0 0 1
pinnumber=3
T 1050 7425 5 8 0 1 0 0 1
pinseq=11
}
P 1000 7200 1300 7200 1 0 1
{
T 950 7200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 7225 5 8 1 1 0 0 1
pinnumber=4
T 1050 7225 5 8 0 1 0 0 1
pinseq=12
}
P 1000 7000 1300 7000 1 0 1
{
T 950 7000 5 8 1 1 0 7 1
pinlabel=GCK1/IO
T 1050 7025 5 8 1 1 0 0 1
pinnumber=5
T 1050 7025 5 8 0 1 0 0 1
pinseq=13
}
P 1000 6800 1300 6800 1 0 1
{
T 950 6800 5 8 1 1 0 7 1
pinlabel=GCK2/IO
T 1050 6825 5 8 1 1 0 0 1
pinnumber=6
T 1050 6825 5 8 0 1 0 0 1
pinseq=14
}
P 1000 6600 1300 6600 1 0 1
{
T 950 6600 5 8 1 1 0 7 1
pinlabel=GCK3/IO
T 1050 6625 5 8 1 1 0 0 1
pinnumber=7
T 1050 6625 5 8 0 1 0 0 1
pinseq=15
}
P 1000 6400 1300 6400 1 0 1
{
T 950 6400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 6425 5 8 1 1 0 0 1
pinnumber=8
T 1050 6425 5 8 0 1 0 0 1
pinseq=16
}
P 1000 6200 1300 6200 1 0 1
{
T 950 6200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 6225 5 8 1 1 0 0 1
pinnumber=9
T 1050 6225 5 8 0 1 0 0 1
pinseq=17
}
P 1000 6000 1300 6000 1 0 1
{
T 950 6000 5 8 1 1 0 7 1
pinlabel=IO
T 1050 6025 5 8 1 1 0 0 1
pinnumber=11
T 1050 6025 5 8 0 1 0 0 1
pinseq=18
}
P 1000 5800 1300 5800 1 0 1
{
T 950 5800 5 8 1 1 0 7 1
pinlabel=IO
T 1050 5825 5 8 1 1 0 0 1
pinnumber=12
T 1050 5825 5 8 0 1 0 0 1
pinseq=19
}
P 1000 5600 1300 5600 1 0 1
{
T 950 5600 5 8 1 1 0 7 1
pinlabel=IO
T 1050 5625 5 8 1 1 0 0 1
pinnumber=13
T 1050 5625 5 8 0 1 0 0 1
pinseq=20
}
P 1000 5400 1300 5400 1 0 1
{
T 950 5400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 5425 5 8 1 1 0 0 1
pinnumber=14
T 1050 5425 5 8 0 1 0 0 1
pinseq=21
}
P 1000 5200 1300 5200 1 0 1
{
T 950 5200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 5225 5 8 1 1 0 0 1
pinnumber=18
T 1050 5225 5 8 0 1 0 0 1
pinseq=22
}
P 1000 5000 1300 5000 1 0 1
{
T 950 5000 5 8 1 1 0 7 1
pinlabel=IO
T 1050 5025 5 8 1 1 0 0 1
pinnumber=19
T 1050 5025 5 8 0 1 0 0 1
pinseq=23
}
P 1000 4800 1300 4800 1 0 1
{
T 950 4800 5 8 1 1 0 7 1
pinlabel=IO
T 1050 4825 5 8 1 1 0 0 1
pinnumber=20
T 1050 4825 5 8 0 1 0 0 1
pinseq=24
}
P 1000 4600 1300 4600 1 0 1
{
T 950 4600 5 8 1 1 0 7 1
pinlabel=IO
T 1050 4625 5 8 1 1 0 0 1
pinnumber=22
T 1050 4625 5 8 0 1 0 0 1
pinseq=25
}
P 1000 4400 1300 4400 1 0 1
{
T 950 4400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 4425 5 8 1 1 0 0 1
pinnumber=24
T 1050 4425 5 8 0 1 0 0 1
pinseq=26
}
P 1000 4200 1300 4200 1 0 1
{
T 950 4200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 4225 5 8 1 1 0 0 1
pinnumber=25
T 1050 4225 5 8 0 1 0 0 1
pinseq=27
}
P 1000 4000 1300 4000 1 0 1
{
T 950 4000 5 8 1 1 0 7 1
pinlabel=IO
T 1050 4025 5 8 1 1 0 0 1
pinnumber=26
T 1050 4025 5 8 0 1 0 0 1
pinseq=28
}
P 1000 3800 1300 3800 1 0 1
{
T 950 3800 5 8 1 1 0 7 1
pinlabel=IO
T 1050 3825 5 8 1 1 0 0 1
pinnumber=27
T 1050 3825 5 8 0 1 0 0 1
pinseq=29
}
P 1000 3600 1300 3600 1 0 1
{
T 950 3600 5 8 1 1 0 7 1
pinlabel=IO
T 1050 3625 5 8 1 1 0 0 1
pinnumber=28
T 1050 3625 5 8 0 1 0 0 1
pinseq=30
}
P 1000 3400 1300 3400 1 0 1
{
T 950 3400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 3425 5 8 1 1 0 0 1
pinnumber=29
T 1050 3425 5 8 0 1 0 0 1
pinseq=31
}
P 1000 3200 1300 3200 1 0 1
{
T 950 3200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 3225 5 8 1 1 0 0 1
pinnumber=33
T 1050 3225 5 8 0 1 0 0 1
pinseq=32
}
P 1000 3000 1300 3000 1 0 1
{
T 950 3000 5 8 1 1 0 7 1
pinlabel=IO
T 1050 3025 5 8 1 1 0 0 1
pinnumber=34
T 1050 3025 5 8 0 1 0 0 1
pinseq=33
}
P 1000 2800 1300 2800 1 0 1
{
T 950 2800 5 8 1 1 0 7 1
pinlabel=IO
T 1050 2825 5 8 1 1 0 0 1
pinnumber=35
T 1050 2825 5 8 0 1 0 0 1
pinseq=34
}
P 1000 2600 1300 2600 1 0 1
{
T 950 2600 5 8 1 1 0 7 1
pinlabel=IO
T 1050 2625 5 8 1 1 0 0 1
pinnumber=36
T 1050 2625 5 8 0 1 0 0 1
pinseq=35
}
P 1000 2400 1300 2400 1 0 1
{
T 950 2400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 2425 5 8 1 1 0 0 1
pinnumber=37
T 1050 2425 5 8 0 1 0 0 1
pinseq=36
}
P 1000 2200 1300 2200 1 0 1
{
T 950 2200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 2225 5 8 1 1 0 0 1
pinnumber=38
T 1050 2225 5 8 0 1 0 0 1
pinseq=37
}
P 1000 2000 1300 2000 1 0 1
{
T 950 2000 5 8 1 1 0 7 1
pinlabel=GSR/IO
T 1050 2025 5 8 1 1 0 0 1
pinnumber=39
T 1050 2025 5 8 0 1 0 0 1
pinseq=38
}
P 1000 1800 1300 1800 1 0 1
{
T 950 1800 5 8 1 1 0 7 1
pinlabel=GTS2/IO
T 1050 1825 5 8 1 1 0 0 1
pinnumber=40
T 1050 1825 5 8 0 1 0 0 1
pinseq=39
}
P 1000 1600 1300 1600 1 0 1
{
T 950 1600 5 8 1 1 0 7 1
pinlabel=GTS1/IO
T 1050 1625 5 8 1 1 0 0 1
pinnumber=42
T 1050 1625 5 8 0 1 0 0 1
pinseq=40
}
P 1000 1400 1300 1400 1 0 1
{
T 950 1400 5 8 1 1 0 7 1
pinlabel=IO
T 1050 1425 5 8 1 1 0 0 1
pinnumber=43
T 1050 1425 5 8 0 1 0 0 1
pinseq=41
}
P 1000 1200 1300 1200 1 0 1
{
T 950 1200 5 8 1 1 0 7 1
pinlabel=IO
T 1050 1225 5 8 1 1 0 0 1
pinnumber=44
T 1050 1225 5 8 0 1 0 0 1
pinseq=42
}
P 1000 800 1300 800 1 0 1
{
T 950 800 5 8 1 1 0 7 1
pinlabel=VCCIO
T 1050 825 5 8 1 1 0 0 1
pinnumber=32
T 1050 825 5 8 0 1 0 0 1
pinseq=43
}

v 20061020 1
B 300 600 1000 800 3 0 0 0 0 0 0 -1 -1 -1 -1 -1
T 300 550 5 10 1 1 0 2 1
refdes=U?
T 300 350 5 10 1 1 0 2 1
device=XC9536
T 200 550 5 10 0 0 0 8 1
copyright=2007 Ben Jackson
T 200 350 5 10 0 0 0 8 1
author=Ben Jackson
T 200 150 5 10 0 0 0 8 1
uselicense=unlimited
T 200 -50 5 10 0 0 0 8 1
distlicense=GPL
T 200 -250 5 10 0 0 0 8 1
description=Xilinx XC9536
T 200 -450 5 10 0 0 0 8 1
footprint=PLCC 44
P 1300 1200 1600 1200 1 0 1
{
T 1250 1200 5 8 1 1 0 7 1
pinlabel=VCCINT
T 1350 1225 5 8 1 1 0 0 1
pinnumber=21
T 1350 1225 5 8 0 1 0 0 1
pinseq=9
}
P 1300 1000 1600 1000 1 0 1
{
T 1250 1000 5 8 1 1 0 7 1
pinlabel=VCCINT
T 1350 1025 5 8 1 1 0 0 1
pinnumber=41
T 1350 1025 5 8 0 1 0 0 1
pinseq=10
}
P 300 1200 0 1200 1 0 1
{
T 350 1200 5 8 1 1 0 1 1
pinlabel=GND
T 250 1225 5 8 1 1 0 6 1
pinnumber=10
T 250 1225 5 8 0 1 0 6 1
pinseq=11
}
P 300 1000 0 1000 1 0 1
{
T 350 1000 5 8 1 1 0 1 1
pinlabel=GND
T 250 1025 5 8 1 1 0 6 1
pinnumber=23
T 250 1025 5 8 0 1 0 6 1
pinseq=12
}
P 300 800 0 800 1 0 1
{
T 350 800 5 8 1 1 0 1 1
pinlabel=GND
T 250 825 5 8 1 1 0 6 1
pinnumber=31
T 250 825 5 8 0 1 0 6 1
pinseq=13
}

Element[0x00000000 "" "" "" 197500 170000 0 0 0 100 0x00000000]
(
	Pad[0 0 0 32500 5000 2000 7000 "" "2" 0x00000100]
	Pad[10000 0 10000 32500 5000 2000 7000 "" "4" 0x00000100]
	Pad[20000 0 20000 32500 5000 2000 7000 "" "6" 0x00000100]
	Pad[30000 0 30000 32500 5000 2000 7000 "" "8" 0x00000100]
	Pad[40000 0 40000 32500 5000 2000 7000 "" "10" 0x00000100]
	Pad[50000 0 50000 32500 5000 2000 7000 "" "12" 0x00000100]
	Pad[60000 0 60000 32500 5000 2000 7000 "" "14" 0x00000100]
	Pad[70000 0 70000 32500 5000 2000 7000 "" "16" 0x00000100]
	Pad[80000 0 80000 32500 5000 2000 7000 "" "18" 0x00000100]
	Pad[90000 0 90000 32500 5000 2000 7000 "" "20" 0x00000100]
	Pad[100000 0 100000 32500 5000 2000 7000 "" "22" 0x00000100]
	Pad[110000 0 110000 32500 5000 2000 7000 "" "24" 0x00000100]
	Pad[120000 0 120000 32500 5000 2000 7000 "" "26" 0x00000100]
	Pad[130000 0 130000 32500 5000 2000 7000 "" "28" 0x00000100]
	Pad[140000 0 140000 32500 5000 2000 7000 "" "30" 0x00000100]
	Pad[0 0 0 32500 5000 2000 7000 "" "1" 0x00000080]
	Pad[10000 0 10000 32500 5000 2000 7000 "" "3" 0x00000080]
	Pad[20000 0 20000 32500 5000 2000 7000 "" "5" 0x00000080]
	Pad[30000 0 30000 32500 5000 2000 7000 "" "7" 0x00000080]
	Pad[40000 0 40000 32500 5000 2000 7000 "" "9" 0x00000080]
	Pad[50000 0 50000 32500 5000 2000 7000 "" "11" 0x00000080]
	Pad[60000 0 60000 32500 5000 2000 7000 "" "13" 0x00000080]
	Pad[70000 0 70000 32500 5000 2000 7000 "" "15" 0x00000080]
	Pad[80000 0 80000 32500 5000 2000 7000 "" "17" 0x00000080]
	Pad[90000 0 90000 32500 5000 2000 7000 "" "19" 0x00000080]
	Pad[100000 0 100000 32500 5000 2000 7000 "" "21" 0x00000080]
	Pad[110000 0 110000 32500 5000 2000 7000 "" "23" 0x00000080]
	Pad[120000 0 120000 32500 5000 2000 7000 "" "25" 0x00000080]
	Pad[130000 0 130000 32500 5000 2000 7000 "" "27" 0x00000080]
	Pad[140000 0 140000 32500 5000 2000 7000 "" "29" 0x00000080]

	)


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