gEDA-user: Missing trace

[Ian Chapman <ichapman@xxxxxxxxxxxx>]

I have almost finished debugging the mostly SMT part of my new board.
(I'll send DJ a photograph once fully assembled).  It's going much
better than I thought it would.  I have three annoyances due to  missing
three traces.  Backtracking to the schematic they are signals between
sheets.  I used the add/components/I/O generic/input_1.sym type of off
page connection.  The net attribute is the same at both ends sig:1 etc.
I have many inter-page signals that are correctly linking my 14 sheets
so I must have that right.  I did have a history of deleting connections
to correct DRC errors but o optimize rats always showed the missing
connections.  Right now o tells me all is okay.  I guess I skipped a
step, any pointers would be welcome.  Regards Ian.



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