Re: gEDA-user: Yet another Icarus question

[Patrick Doyle <wpdster@xxxxxxxxx>]

On Wed, Aug 4, 2010 at 11:46 AM, Larry Doolittle
<ldoolitt@xxxxxxxxxxxxxxx> wrote:
> On Wed, Aug 04, 2010 at 10:58:51AM -0400, Patrick Doyle wrote:
>> Can anybody tell me if the following is an Icarus feature or a Verilog
>> feature.
>
> Verilog.  Probably.
>
>> reg [5:0] offset;
>> reg [9:0] enablemask;
>>    initial begin
>>      enablemask = 10'b00000_00110;
>>      offset     = 0;
>>      $display("%b", {enablemask, (16'h0 +  8'h80 + offset )});
>>      $display("%b", {enablemask, (16'h0 + (8'h80 + offset))});
>>    end
>
> This can be explained as long as the default addition order
> in Verilog is left-to-right, thus
> "16'h0 +  8'h80 + offset"  is defined as "(16'h0 +  8'h80) + offset".
>
> 16'h0 +  8'h80  is 17 bits wide, to account for carry.
OK, now you've got me curious... and I'm now convinced it's a bug in
Icarus.  I tracked down a copy of the Verilog standard (IEEE Std
1364-2005).  According to what I read:

"The expression i op j where op is: + - * / % & |  ^ ^~ ~^ has a bit
length equal to max(L(i), L(j))

Where L(i) represents the length of the operand represented by i"


From that, I would say that 16'h0 + 8'h80 should be 16 bits wide.
There is no carry.  Is that right Cary?  (Sorry, I couldn't resist.)

I think I'll go file the bug report now.  The worst that it will
happen is that it will be rejected.

--wpd


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