gEDA-user: Yet another Icarus question

[Patrick Doyle <wpdster@xxxxxxxxx>]

Can anybody tell me if the following is an Icarus feature or a Verilog
feature.  I would expect the two $display statements to show the same
results.  For some reason, the first one expands the result to 27 bits
instead of the 26 bits I would have expected.  The only difference
(hopefully) between the two lines of code is the addition of a set of
parentheses.

Obviously, I don't really think this is a "feature", but is likely to
be a "bug".  But before I make such hasty accusations, I thought I
would ask for some other opinions (knowing full well that Cary and
Stephen follow this list :-))  I am running:

Icarus Verilog version 0.10.0 (devel) (s20090923-223-g9fbb12d)

If it is agreed that this is a bug, I can file the report.

--wpd

module check_this;

reg [5:0] offset;
reg [9:0] enablemask;
   initial begin
     enablemask = 10'b00000_00110;
     offset     = 0;
     $display("%b", {enablemask, (16'h0 +  8'h80 + offset )});
     $display("%b", {enablemask, (16'h0 + (8'h80 + offset))});
   end
endmodule // check_this


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