Re: gEDA-user: OT Verilog syntax question

[Patrick Doyle <wpdster@xxxxxxxxx>]

On Tue, Aug 3, 2010 at 12:59 PM, Stephen Williams <steve@xxxxxxxxxx> wrote:
>
> I'm a little surprised that Icarus Verilog doesn't already pay
> attention to the "4" in your "%4b". In any case, this should do
> the trick for you:
>
>   integer result;
>     ... $display("%b", result[3:0]); ...
>
Oh, of course....

But now, just to make things even more complicated, what I _really_
wanted to display was

$display("%10b", $rtoi[some_floating_expr_less_than_1024));

...which I could probably do also with your wire trick.

wire [9:0] tmp = $rtoi(whatever);

Regardless, I'm getting the impression that there is no simple way to
cast an integer expression to a bit vector.  I wonder why I thought
there was... probably was just wishful thinking.

--wpd


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