gEDA-user: OT Verilog syntax question

[Patrick Doyle <wpdster@xxxxxxxxx>]

Sorry to pester you folks with this, but I'm not sure whom else to ask.

I have some verilog test code in which I would like to display an
integer value, which is known to be between 0 and 15, as a binary
vector, i.e.

integer result;
$display("%4b", result);

of course I get a 64 bit vector displayed.

Is there any way to cast my integer variable "result" as a 4 bit
vector just for use in a $display statement?

Thanks for any tips you can give me.

--wpd


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