Re: gEDA-user: OT Verilog syntax question

[Patrick Doyle <wpdster@xxxxxxxxx>]

On Tue, Aug 3, 2010 at 12:33 PM, Larry Doolittle
<ldoolitt@xxxxxxxxxxxxxxx> wrote:
> On Tue, Aug 03, 2010 at 09:12:00AM -0400, Patrick Doyle wrote:
>> I have some verilog test code in which I would like to display an
>> integer value, which is known to be between 0 and 15, as a binary
>> vector, i.e.
>>
>> integer result;
>> $display("%4b", result);
>>
>> of course I get a 64 bit vector displayed.
>>
>> Is there any way to cast my integer variable "result" as a 4 bit
>> vector just for use in a $display statement?
>
> integer result;
> reg [3:0] result_disp;
> always @(foo) begin
>        result_disp = result;
>        $display("%4b", result_disp);
> end
>
> Simpler still is to use reg [3:0] result in the first place,
> but maybe that breaks other parts of the code.
Thanks Larry,
This is in some debug code where result is already an integer.  I
could adapt your solution to something like:

reg [3:0] result_disp;
always @(result) result_disp <= result;

and in my main test script display result_disp instead of result.  But
that seems clumsy and awkward.  I thought I had seen once a way to
cast an integer variable to a vector with some sort of
{4`width{result}} kind of silly syntax.  (I just made that one up.)
But I can't recall it, nor can I convince my buddy Google to find it
for me.  It is quite likely that I just dreamed this up and that it's
not a feature of the language.

But I figured I'd ask this pool of experts before I gave up.

--wpd


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