Re: gEDA-user: OT Verilog syntax question

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

On Tue, Aug 03, 2010 at 09:12:00AM -0400, Patrick Doyle wrote:
> I have some verilog test code in which I would like to display an
> integer value, which is known to be between 0 and 15, as a binary
> vector, i.e.
> 
> integer result;
> $display("%4b", result);
> 
> of course I get a 64 bit vector displayed.
> 
> Is there any way to cast my integer variable "result" as a 4 bit
> vector just for use in a $display statement?

integer result;
reg [3:0] result_disp;
always @(foo) begin
	result_disp = result;
	$display("%4b", result_disp);
end

Simpler still is to use reg [3:0] result in the first place,
but maybe that breaks other parts of the code.

   - Larry


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