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Re: gEDA-user: Yet another Icarus question

On 08/04/2010 09:58 AM, Patrick Doyle wrote:

Can anybody tell me if the following is an Icarus feature or a Verilog
feature.  I would expect the two $display statements to show the same
results.  For some reason, the first one expands the result to 27 bits
instead of the 26 bits I would have expected.  The only difference
(hopefully) between the two lines of code is the addition of a set of
parentheses.


It's not very easy to find bugs in Icarus verilog.



module check_this;

reg [5:0] offset;
reg [9:0] enablemask;
    initial begin
      enablemask = 10'b00000_00110;
      offset     = 0;
      $display("%b", {enablemask, (16'h0 +  8'h80 + offset )});
      $display("%b", {enablemask, (16'h0 + (8'h80 + offset))});
    end
endmodule // check_this


Hmmm... carry?  Verilog is about wires and logic gates and definitely creates carries and keeps them.
The numbers you added in (16'h0 +  8'h80 + offset ) add up to less than 16 bits wide.
offset is not defined as a vector of wires.  That's probably where some definition gets you.

How wide is offset?  Default.
Default = ?  16?  Maybe that is generating a carry of 0, and keeping track of it where you expected it to be thrown away
as in a high level language..  Verilog works in parallel, which seems like a high level language feature, but really
it is assembler language for wires.
If a carry of zero is doing this, you would just print the most significant digits of your add, the rightmost ones.

A carry of zero doesn't happen in real wires, so maybe I'm all wrong.

John


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