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Re: gEDA-user: DRC rule structure




Actually, I don't think that's true:

Suppose I have a trace whose clearance is set to 2.5mm - if I lay any component
too close while the real-time DRC is running, how can it know that it's breaking
a rule without re-checking the clearance for every object on the PCB?
By checking exactly the object you are currently trying to place against the traces in vicinity,
that can be found by bounding-box intersection.


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