gEDA-user: using gschem to generate vhdl

[Ales Hvezda <ahvezda@seul.org>]

[ Ales here, I'm reposting this since majordomo didn't recognize the
  e-mail as being subscribed to the geda-dev mailinglist. Some of these
  are a few weeks old, since they got misplaced.  Sorry. ]

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Hallo!

while looking for a replacement for synopsys' old sge I came across gschem
and gnetlist which both look very promising to me.

What I intend to do here is (for a stundent practical course) use gschem
for hierarchical schematics and automatically generate vhdl via gnetlist.
I managed to get this done, but it seems there are some minor feature are
still missing or perhaps it's me who doesn't know how to do these things
in geda:

--- when doing hierarchical designds, the component declarations are empty:

    COMPONENT xor
    END COMPONENT ;

  vhdlan complains about a syntax error here, I'm not sure if this is
  because "xor" is not declared in any lib or because a port declaration
  is missing (sge always generates a port here).

--- I found out that by adding a "width" attribute to ports vhdl generates
  nice bus port declarations - but I wonder how gschem handles busses.
  is there some way for a symbol to have "bus" pins, e.g. 16 bits wide?

  Is it possible to access single bits of a bus - I'm thinking of
  sge here which used the convention that if a net is named "bus[5]"
  this means this net is connected to bit #6 of "bus"

--- is there a conventient way to generate a symbol representing a component
  design in gschem? I'm thinking of a scheme script of gnetlist which
  extracts all ports and generates a rectangular symbol with all the pins
  which could then be used in the next hiearchical level to embed a
  component.

Any statements about the current status of the above issues is very
appreciated. I'd just like to know if anybody is already working on these
issues (or perhaps has already solved them), if not I'm willing to work on
this myself.

Keep up the good work,

   Guenter

----
time is a funny concept