gEDA-user: Icarus Verilog and Xilinx CoreGen questions

["John McCaskill" <john@mccaskill.com>]

First, to Stephen Williams, Thank you very much for Icarus Verilog. I have
been using it for about two months now, and I think it is great.  I have
been able to accomplish a lot of work with it.

Now for my question, has anyone used Icarus to simulate a design that
contains a Xilinx CoreGen module using the XilinxCoreLib library?  I have
searched the web, and I can not find any mention of this.  Is that something
that Icarus supports, or plans to support?

 I have started to try to use Icarus to simulate a design that I am using a
CoreGen module in, and I am running into problems.  Specifically, I get
different results out when I run the same test bench on both Icarus and
ModelSim, with Icarus returning Xs and ModelSim returning what I expect.  I
also tried simulating a large existing design that used multiple CoreGen
modules, and it will not make it past compiling.

If anyone has simulated a CoreGen module with Icarus, would you tell what
you had to do to get it to work?

I am using the verilog-0.7.20031202-0.i386.rpm build, but I also tried the
latest precompiled Windows version, and had even more problems.

I am working on getting a simple example of this to upload as a bug report,
but I would like to know about any experience that others may have had
trying to do this.

Regards,

John McCaskill