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Re: gEDA-user: Unexplained Icarus warning

David Howland wrote: 
The test code that produces this is as follows:
-------------------------8<------------------------
module test (D, clk, en, Q);
  input   D, clk, en;
  output  Q;
  reg Q;
  always @(clk)        // this is line 8
  begin
    if(en==1)
    begin
      Q = D;
    end
  end
endmodule
------------------------->8------------------------
It's perfectly valid Verilog code, but its not being synthesized??
What's up with that?


It's valid verilog, but kind-of a weird device you are modeling
there. Are you really trying to make a D-type flip-flop that
loads on both edges of the clock input? The Icarus Verilog synth-
esizer doesn't quite know what to make of it, so it leaves it as
behavioral code.

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."