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gEDA-user: ANNOUNCE: MyHDL 0.4.1 with cver support
- To: geda-user@xxxxxxxx
- Subject: gEDA-user: ANNOUNCE: MyHDL 0.4.1 with cver support
- From: Jan Decaluwe <jan@xxxxxxxxxxxxxxx>
- Date: Fri, 31 Dec 2004 01:04:01 +0100
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- Delivered-to: geda-user@seul.org
- Delivery-date: Thu, 30 Dec 2004 18:10:29 -0500
- Organization: resources
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MyHDL is a Python package for using Python as a hardware description
and verification language. MyHDL 0.4.1 is now available at:
http://sourceforge.net/project/showfiles.php?group_id=91207
MyHDL 0.4.1 release notes:
* Maintenance release that solves most outstanding issues
and implements some feature requests.
See the SourceForge Bug and RFE Trackers for details.
More info can also be found on the mailing list.
* Added cosimulation support for the cver Verilog simulator.
Regards,
Jan
--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Using Python as a hardware description language:
http://jandecaluwe.com/Tools/MyHDL/Overview.html