Re: gEDA-user: mosfet design help

["John Luciani" <jluciani@xxxxxxxxx>]

On 12/3/06, gene glick <carzrgr8@xxxxxxxxxxxxx> wrote:
> I want to build a mosfet inverter that also translates voltages. Pretty
> much standard mosfet inverter, nmos is lower transistor, pmos is upper
> transistor.  The upper pmosfet Vsource is +5VDC, and mosfet Vsource is
> -5VDC.  But, the gate voltage is +/- 50VDC.
>
> Although the gate voltage exceeds the turn-on threshold of the mosfet's
> - but does it violate any max values for Vgs or Vgd?  At these levels,
> the Vgs is going to around 55 volts.  The Vds is fine, and is easy to
> select a transistor for these levels.
>
> It's not clear to me what the Vgs and Vgd maximums are, from reading
> various mosfet data sheets. Any help?

All of the datasheets that I have seen have an "Absolute Maximum Ratings"
table. I have not seen FETs with that high a Vgs rating.

If an attenuation scheme doesn't work for your circuit you may want to look at
optoisolation. If you are running at low frequency you could look at the IR
PVI drivers.

(* jcl *)

--
http://www.luciani.org


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