Re: gEDA-user: mosfet design help

[Dan McMahill <dan@xxxxxxxxxxxx>]

gene glick wrote:
> I want to build a mosfet inverter that also translates voltages. Pretty 
> much standard mosfet inverter, nmos is lower transistor, pmos is upper 
> transistor.  The upper pmosfet Vsource is +5VDC, and mosfet Vsource is 
> -5VDC.  But, the gate voltage is +/- 50VDC.
>
> Although the gate voltage exceeds the turn-on threshold of the mosfet's 
> - but does it violate any max values for Vgs or Vgd?  At these levels, 
> the Vgs is going to around 55 volts.  The Vds is fine, and is easy to 
> select a transistor for these levels.
>
> It's not clear to me what the Vgs and Vgd maximums are, from reading 
> various mosfet data sheets. Any help?

usually the datasheets are pretty clear about the max gate to source 
voltage.  If you have a pointer to a datasheet, that would help.  I'll 
bet that +/- 50 V is enough to blow up most FET's that you'll find.  For 
going from +/- 50V swing to +/- 5V there are a lot of things you could 
do depending on the speed at which it needs to work.  You could make a 
resistive divider and supplement it with a diode clamp to make sure you 
never exceed some maximum tolerable swing at the output.  You might 
still want to follow this with a circuit like you describe.

Be aware that even if your FET's can take the Vgs, think for a bit about 
what the time domain output of the inverter will be when you put 100V 
steps into the input.  This is especially a concern if you have a fast 
edge.  Hint, don't ignore Cgd.

-Dan






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