Re: gEDA-user: Weirdness with Design Rule Checker

[DJ Delorie <dj@xxxxxxxxxxx>]

http://www.delorie.com/pcb/tmp/george.html

Left: Note that the trace has a clearance approximately the size of the via,
and it wipes out part of the thermal.  The clearance is causing DRC
problems as it's trying to clear copper away from the via as well ('K'
on the line clears it completely away from the via).

Right: A better solution is to let the line join with the polygon
('J') and change the via so that the line doesn't interfere with it
(Thermal Tool, shift-click).

Side note: if this is going to be a manufactured board (vs
home-etched), you can use the thermal tool to remove the thermals from
the vias, resulting in a solid connection to the planes.


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