gEDA-user: wire real bus in Icarus Verilog

[Patrick Doyle <wpdster@xxxxxxxxx>]

Hi Folks!

How much work would be involved in extending the extended data types
in Icarus (http://www.geda.seul.org/wiki/geda:icarus_extensions) to
support a bus of wire reals, e.g.

wire real [9:0] realbus;

wire real x = realbus[0];
wire real y = realbus[1];
etc...

I can poke around and see what I might be able to do with this, but I
figured I'd better ask the experts first.

I'm not familiar with SystemVerilog, so I don't know if this is
compatible with the standard or not.

--wpd


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