Re: gEDA-user: wire real bus in Icarus Verilog

[Patrick Doyle <wpdster@xxxxxxxxx>]

On Sat, Dec 18, 2010 at 4:39 PM, Patrick Doyle <wpdster@xxxxxxxxx> wrote:
> Hi Folks!
>
> How much work would be involved in extending the extended data types
> in Icarus (http://www.geda.seul.org/wiki/geda:icarus_extensions) to
> support a bus of wire reals, e.g.
>
> wire real [9:0] realbus;
>
> wire real x = realbus[0];
> wire real y = realbus[1];
> etc...
>
> I can poke around and see what I might be able to do with this, but I
> figured I'd better ask the experts first.
>
> I'm not familiar with SystemVerilog, so I don't know if this is
> compatible with the standard or not.
>

Here's a trivial example of what I'd like to be able to do...

module realtest;
wire real [1:0] outbus;
reg [1:0] inbus;

integer   i;
   bus_writer  u3(outbus, inbus);

   initial begin
     for (i = 0; i < 5; i = i + 1) begin
       #1 $display("i = %0d, inbus=%b, outbus[0] = %f, outbus[1] = %f",
		   i, inbus, outbus[0], outbus[1]);
       inbus <= i;
     end
   end
endmodule // realtest

module bus_writer(out, in);
output [1:0] out;
input [1:0]  in;

real out_r[1:0];
wire real [1:0] out;

   always @(in)
     case (in)
       2'b00: begin
	 out_r[0] = 10;
	 out_r[1] = 20;
       end

       2'b01: begin
	 out_r[0] = 30;
	 out_r[1] = 40;
       end

       2'b10: begin
	 out_r[0] = 50;
	 out_r[1] = 60;
       end

       2'b11: begin
	 out_r[0] = 70;
	 out_r[1] = 80;
       end

       default: begin
	 out_r[0] = 0;
	 out_r[1] = 0;
       end
     endcase // case (in)
   assign out[0] = out_r[0];
   assign out[1] = out_r[1];
endmodule // bus_writer


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