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Hello,
Using Icarus Verilog, the following code does
not
elaborate.
------------------------------------------------------
`timescale 1ns/1ns
module testtask ( a, b, c, z );
input [ 5:0 ] a, b, c;
output [ 5:0 ] z; wire [ 5:0 ]
s1;
assign z = s1 & c;
blah ( a, b, s1 ); task blah; input [ 5:0 ] a, b;
output [ 5:0 ] c; begin
c = a ^ b;
end
endtask endmodule
------------------------------------------------------ The message that I get is:
testtask.v:11: error: Unknown module type:
blah
Elaboration failed
Does anyone know why iverilog does not
recognize the
'blah' task where it
is being called? Note, this is the
case
whether I place the
call to blah before or after the task
declaration.
[I do not have access to a commercial verilog
simulator,
so I cannot verify that my code is not the problem.]
Thanx,
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