[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

gEDA-user: putting it all together



Gentlemen:
    I've spent a few months trying to get my hands around undestanding the design flow sufficient to understand how to get an IC designed. Let me tell you where I am and then where my missing piece seems to be. I can take Verilog files with Icarus and compile to the fpga target and I get an a.out that makes sense in that it defines INV, AND, OR, DFF and others. I can also take Magic, load a padframe into it and put cells such as INV, AND, OR, DFF and others and that makes sense mostly. I can see how IRSIM & Spice fit into the equation as I can see the .sim and .spice files that ext2sim and ext2spice create and they seem to make sense. I can even run IRSIM and see an inverter or a gate toggle as extracted from a Magic layout. I can also see that Magic appears to have some routing capability with iroute & garouter, but although I havent figured out how to run these functions yet, I can at least imagine that I should be able to get them to do something.
 
    The missing piece seems to be the netlist in the middle. Somehow, there needs to be a way to take the netlist expressed from Icarus with its associated INV, AND, OR, DFF SYM's and produce a netlist that is an input to Magic that allows Magic to then load cells from its library (yes, I have found a couple of libraries, one at mosis.org and the other at University of Kansas). Admittedly, I may have to change either the netlist or the cells to make the label names match, but I can see how that could be accomplished. After that, it is necessary to load all those cells into the middle of a blank piece of silicon and allow iroute, garouter or something similar to then route the interconnections between the cells as described in the netlist.
 
    I did take a side trip with Electric a month or so ago, and although I can compile its automotive speed controller IC sample from source with its library and its silicon compiler and it even does load in cells from its version of the mosis library, place them in rows and connect them up, it is VHDL and I am working in Verilog. So, that and the fact that Magic appears to be more prevalent then Electric has caused me to come back to Magic again. I have trouble believing that Electric can do something that Magic cannot do, rather, I suspect that my understanding of Magic is not complete enough yet.
 
    I am hoping that someone will help me understand how this missing piece might work and shed some helpful comments on my path towards enlightenment (IC speaking).
 
 
Charles Krinke
http://home.pacbell.net/cfk
cfk@pacbell.net