Re: gEDA-user: putting it all together

[cfk <cfk@pacbell.net>]

Dear Steve:
    Thank you very much for replying to my question. I did try to think it
out a bit before my post. At this point, I am looking at the output of
a -tfpga of a modest Verilog source, with the SYM's BUF, INV, AND, DFF
(which I can grok to a particular MOSIS cell library implementation) and EQN
(which I dont grok to a cell implementation yet). I can see the various O,
I, Q, D & C pins defined. I can also see in one of the two libraries I have
found (one from Mosis, the other from Univ Kansas at
http://www.rsl.ukans.edu~mlinhard/magic ) the pins Prof Evans has defined
which are names like for instance on one of his inverters A1 for input and O
for output, so I could see making Icarus either output that sort of thing
from d-generic.c or making a new target in Icarus. I am holding that project
in abeyance for the nonce until I can understand the next step as changing
Icarus to output a netlist compatible with a particular library is for
naught if we cant place and route the cells in accordance with the netlist.

    I have looked at Electric a bit and I can see something called QUISC for
Queens University Integrated Silicon Compiler. That looks very interesting
as it can take a netlist (albeit from VHDL, but nonetheless a netlist), and
define rows for the cells with a modest dialog box and widths for the
metal1/metal2 traces and it does make a nice stab at producing a reasonable
implementation of an automotive speed control IC. By the say Steve, Steve
Rubin's reply to my question about Verilog to Electric was to modify Icarus
to do just that.

    Near as I can tell, although Magic has some routing capability, it would
need to be hand fed not only a netlist, but a .mag file with locations of
the various library cells as subcells along with the netlist in order to get
to the placing of logic cell items. Basically, in examing a .mag file, I can
see statements like "use cellx", "transform to x,y", so I can imagine how
some of that might be done.

    I really am trying to figure out if Magic is just missing this whole
thing, or if there is another package that can sit between Icarus and Magic
in order to do the placement so that Magic can then do the routing. I am
thinking that there must be some sort of code generator out there allready,
if nothing else, then perhaps the QUISC could be interfaced to Magic in
order to give it a bit placing functionality.



----- Original Message -----
From: "Stephen Williams" <steve@icarus.com>
To: <geda-user@seul.org>
Sent: Saturday, February 22, 2003 3:21 PM
Subject: Re: gEDA-user: putting it all together


>
> cfk@pacbell.net said:
> > I am studying the use of Icarus Verilog to create an RTL netlist. From
> > that netlist, which has INV, OR, NAND, etc defined, I am trying to
> > understand how to flow the netlist into Magic.
>
> The best way to get from Verilog to MAGIC is to write a code generator
> that generates the appropriate netlist format. The ivl_target API
> actually communicates the compiled design with LPM (approximately)
> level devices, which the code generators then write into real world
> netlist/library combinations.
>
> The newer -tfpga supports Xilinx Virtex parts more directly then the
> -txnf code generator you are apparently using. The EDIF that comes
> out of that code generator can be handed directly to the Xilinx tools
> for map/par. The sqrt-virtex.v example demonstrates this.
>
> ASIC based libraries are different from FPGA parts libraries, so
> hacking the -tfpga code generator would not be ideal.
>
> It would be fairly nifty if someone would like to take the time to
> write a code generator for the libraries supported by MOSIS. Writing
> a code generator is easier then writing a synthesizer (the synthesis
> is already done) and even easier then writing the design for your
> chip; but harder then writing a simple set of printfs.
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> steve at picturel.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
>
>