RE: gEDA-user: putting it all together

["Jason Doege" <jdoege@inovys.com>]

If someone wanted to take a whack at normalizing a library, we could
eliminate most of the optimization issues. "Logical Effort" by
Sutherland, Sproull and Harris describes some of how this could be done.
I believe the many hundred thousand dollar tool Magma uses this
technique at the core of it's technology. We would need to know what the
design rules were for the library and process.

The basic technique is to determine what the normalized delay is for all
sizes of a particular type of gate when driving an appropriate load.
Then you make one generic version of that gate for synthesis purposes.
The delay cost is then described by some functions in that book. The
synthesis tool no longer has to concern itself with sizing gates as that
will be done after the synthesis step, along with appropriately sizing
the wire. It just has to select the right gate types for minimal delay
cost. Wire load and gate size are represented in the abstract,
normalized delay cost. I've heard that you get to within 10% of optimal
timing this way and always report a number that is conservative relative
to actual physical implementation. (But we all know where marketing
numbers come from :-)

The main thing, here is that you can let a synthesizer do what it does
well, that is minimize and map logic, then you can let a physically
knowledgable tool optimize the transistors after the fact and chances
are you will get a good enough product that you won't have to iterate.
Since I don't think Icarus Verilog presently supports the idea of timing
models, wire-load rules, multiple gates sizes, or even how to map to odd
logic functions like AOIs or say, selecting an 8 input AND instead of 7
2 input ANDs, this might be a good way to get to a useful end product.

Best regards,
Jason

-----Original Message-----
From: Evan Lavelle [mailto:eml@riverside-machines.com] 
Sent: Wednesday, February 26, 2003 3:48 AM
To: geda-user@seul.org
Subject: Re: gEDA-user: putting it all together


Jason Doege wrote:
> In particular, LUTs will have to be re-mapped to boolean functions.
> 
> The person who first requested this got a little irritated when 
> pressed about optimization, but I think there will need to be at least

> a minimum cost analysis done for proper cell selection. Then there is 
> the issue of legal cell selection which is to say cell size selection.

> Some combinations are simply not allowed such as too weak gates 
> driving too much capacitance. Then there is the issue of static 
> timing. Unlike with flip flops, these circuits do not have pre-routed 
> clock trees and so won't even work unless some clock-tree synthesis is

> included in the flow (unless we intend for people to hand create 
> these.) All this and probably much more I'm neglecting is required 
> just to get to a logically functional circuit.
> 
> Best regards,
> Jason

I agree that this is (incredibly) dificult - if Magic doesn't do clock 
tree synthesis and cell sizing, then you can forget it. However, I think

that a simple library-specific netlist - Artisan or Virage - would be 
very useful (isn't Artisan doing free libraries now?). With a netlist 
you could:

1  Do a gate count - easy
2  Do some power analysis? Is there some free code out there that could 
help with this?
3  Do a noddy fmax calculation - Ok, to within maybe a factor of 2

These 3 numbers would be *very* useful and would let you do a proof of 
concept without spending $40k - $100K on a synthesiser. If someone wants

to do this, then I could probably put in some time to help.

Evan