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RE: gEDA-user: putting it all together
- To: <geda-user@seul.org>
- Subject: RE: gEDA-user: putting it all together
- From: "Jason Doege" <jdoege@inovys.com>
- Date: Wed, 26 Feb 2003 08:26:54 -0800
- Delivered-to: archiver@seul.org
- Delivered-to: geda-user-outgoing@seul.org
- Delivered-to: geda-user@seul.org
- Delivery-date: Wed, 26 Feb 2003 11:26:59 -0500
- Reply-to: geda-user@seul.org
- Sender: owner-geda-user@seul.org
- Thread-index: AcLdfDEcuxs5m/1nQDuv5w0sS6p4HAAN24wA
- Thread-topic: gEDA-user: putting it all together
'doh, I had sequential logic on the brain I meant to say:
"Unlike with FPGA's...", not "Unlike with flip flops..."
Jason
Jason Doege wrote:
...
> driving too much capacitance. Then there is the issue of static
> timing. Unlike with flip flops, these circuits do not have pre-routed
> clock trees and so won't even work unless some clock-tree synthesis is
> included in the flow (unless we intend for people to hand create
> these.) All this and probably much more I'm neglecting is required
> just to get to a logically functional circuit.
...