Re: gEDA-user: putting it all together

[cfk <cfk@pacbell.net>]

Dear Jason:
    Actually, compiling a set of Verilog code that is known to compile with
Xilinx ISE does generate proper non-LUT symbols. I can see INV, AND, OR and
so forth. I believe that the LUT's come from Xilinx libraries, although I
could be wrong on that point. I have found several cell libraries available
on the net, they all seem to have a common MOSIS root "rooted" somewhere in
antiquity. The one that is currently on the top of my thinking is the one at
University of Kansas (use google, search on "cell libraries") and it seems
based on the one at the University of Mississippi.

    It also seems that the placement issue can be modularized. A clock tree
can be designed and placed seperately from various Verilog modules (or
subsystems). It would seem that subsystems (or modules) would need to be
placed in groups with their associated RatsNests displayed so that the
members of the group can be re-arranged for appropriate signal placement.
After the modules have been placed, then the routing can proceed. I know
some of this borrows from PCB layout concepts, but I think it is basically a
very similar problem

Charles

----- Original Message -----
From: "Jason Doege" <jdoege@inovys.com>
To: <geda-user@seul.org>
Sent: Tuesday, February 25, 2003 1:39 PM
Subject: RE: gEDA-user: putting it all together


In particular, LUTs will have to be re-mapped to boolean functions.

The person who first requested this got a little irritated when pressed
about optimization, but I think there will need to be at least a minimum
cost analysis done for proper cell selection. Then there is the issue of
legal cell selection which is to say cell size selection. Some
combinations are simply not allowed such as too weak gates driving too
much capacitance. Then there is the issue of static timing. Unlike with
flip flops, these circuits do not have pre-routed clock trees and so
won't even work unless some clock-tree synthesis is included in the flow
(unless we intend for people to hand create these.) All this and
probably much more I'm neglecting is required just to get to a logically
functional circuit.