In particular, LUTs will have to be re-mapped to boolean functions.
The person who first requested this got a little irritated when pressed
about optimization, but I think there will need to be at least a minimum
cost analysis done for proper cell selection. Then there is the issue of
legal cell selection which is to say cell size selection. Some
combinations are simply not allowed such as too weak gates driving too
much capacitance. Then there is the issue of static timing. Unlike with
flip flops, these circuits do not have pre-routed clock trees and so
won't even work unless some clock-tree synthesis is included in the flow
(unless we intend for people to hand create these.) All this and
probably much more I'm neglecting is required just to get to a logically
functional circuit.
Best regards,
Jason
I agree that this is (incredibly) dificult - if Magic doesn't do clock
tree synthesis and cell sizing, then you can forget it. However, I think
that a simple library-specific netlist - Artisan or Virage - would be
very useful (isn't Artisan doing free libraries now?). With a netlist
you could: